GRADUATE STUDENT SUPERVISION:

 

Postdoctoral Student Supervised: 1

 

1. B. Ramkumar, PROPERCAD: A Portable Object Oriented Parallel Environment for VLSI CAD, Jan. 1991-Aug. 1992.

 

Ph.D. Theses Supervised: 35

 

1. A. L. N. Reddy, “Parallel Input/Output Architectures for Multiprocessors,” CRHC-90-5, UILU-ENG-90-2235, UIUC Ph.D. Thesis, ECE Department, May 1990.

 

2. R. M. Kling  “Optimization by Simulated Evolution and Its Application to Cell Placement,” CRHC-90-7, UILU-ENG-90-2237, UIUC Ph.D. Thesis., ECE Department, May 1990.

 

3. S. Patil  “Parallel Algorithms for Test Generation and Fault Simulation,” CRHC-90-12, UILU-ENG-90-2245, UIUC Ph.D. Thesis, ECE Department, August 1990.

 

4. K. P. Belkhale  “Parallel Algorithms for Computer-Aided Design with Applications to Circuit Extraction,” CRHC-90-15, UILU-ENG-90-2252, UIUC Ph.D. Thesis, CS Department, August 1990.

 

5. V. Balasubramanian, “Analysis and Synthesis of Algorithm Based Error Detection in Multiprocessors,” CRHC-91-6, UIUC PhD Thesis, ECE Department, Feb. 1991.

 

6. R. Brouwer,  “Parallel Algorithms for Placement and Routing,” CRHC-91-2, UIUC PhD Thesis, ECE Department, Feb. 1991.

 

7. J. M. Hsu, “Performance Evaluation and Hardware Support of Message Communication in Distributed Memory Multicomputers,” CRHC-91-5, UIUC PhD Thesis, CS Department, Feb. 1991.

 

8. M. Gupta, “Automated Data Partitioning in Distributed Memory Multicomputers,” UIUC PhD Thesis, CS Department, September 1992.

 

9. S. Kim, “Novel Algorithms for Cell Placement and Their Parallel Implementations,” UIUC PhD Thesis, ECE Department, July 1993.

 

10. K. De, “Parallel Algorithms for Logic Synthesis,” UIUC PhD Thesis, ECE Department, September 1993.

 

11. S. Parkes, “A Class Library Approach to Concurrent Object-Oriented Programming with Applications to VLSI CAD,” UIUC Ph.D. Thesis, ECE Department, September 1994.

 

12. M. Peercy, “Design of Hardware and Software Reconfiguration Strategies for Distributed Memory Multicomputers, “, UIUC Ph.D Thesis, ECE Department, September 1994.

 

13. A. Lain, “Compiler and Runtime System for Supporting Irregular Applications in Distributed Memory Multicomputers,” UIUC Ph.D. Thesis, CS Department, October 1995.

 

14. A. Roy-Chowdhury, “Manual and Compiler Assisted Techniques for Synthesizing Fault-Tolerant Parallel Programs,” UIUC Ph.D. Thesis, ECE Department, November 1995.

 

15. S. Ramaswamy, “Simultaneous Exploitation of Task and Data Parallelism in Regular Scientific Applications,” UIUC Ph.D. Thesis, ECE Department, January 1996.

 

16. D. Palermo, “Compiler Techniques for Optimizing Communication and Data Distribution in Distributed Memory Multicomputers,” UIUC Ph.D. Thesis, ECE department, May 1996.

 

17. J. Chandy, “Parallel Algorithms for Standard Cell Placement Using Simulated Annealing,” UIUC Ph.D. Thesis, ECE department, July 1996.

 

18. E. Su, “A Compilation Framework for Distributed Memory Message-Passing Multicomputers,” UIUC Ph.D. Thesis, ECE department, Mar. 1997.

 

19. J. Holm, “Performance Evaluation of Message-Driven Parallel Applications on General-Purpose Multiprocessors,” UIUC Ph.D. Thesis, ECE department, Apr. 1997.

 

20. V. Krishnaswamy, “Parallel Algorithms for VHDL Simulation,” UIUC Ph.D. Thesis, CS department, Apr. 1997.

 

21. Z. Xing, Novel Algorithms for Placement and Routing and their Parallel Implementations, UIUC Ph.D. Thesis, CS department, Jul. 1997.

 

22. D. Krishnaswamy, “Parallel Algorithms for Test Generation and Fault Simulation,” UIUC Ph.D. Thesis, ECE department, Jul. 1997.

 

23. G. Hasteer, “Equivalance Checking in a Modular Checking Framework,” UIUC Ph.D. Thesis, CS department, Dec. 1997.

 

24. S. Roy, “Low Power Driven Sequential Algorithms for Combinational and Sequential Circuits,” UIUC Ph.D. Thesis, ECE Department, Aug. 1998.

 

25. P. Prabhakaran, “Improved Algorithms for High-Level Synthesis and Their Parallel Implementations,” UIUC Ph.D. Thesis, CS department, Oct. 1998.

 

26. D. Chakrabarti, “Design and Evaluation of a Uniform Compilation Framework for Hybrid Applications, “ Northwestern Univ. ECE Department, June 2000.

 

27. Y. Yuan, “Novel Algorithms for 3-D Capacitance Extraction and the Parallel Implementations,” Northwestern Univ. ECE Department, June 2000.

 

28. M. Haldar, “Optimized Hardware Synthesis for FPGAs,” Northwestern University, ECE Department, Aug. 2001.

 

29. A. Nayak, “Automatic Parallelization and Optimizations for Synthesizing MATLAB Programs on Multi FPGA Systems,” Northwestern University, ECE Department, Aug. 2001.

 

30. A. K. Jones, “PACT HDL: A C Compiler with Power and Performance Optimizations,”Northwestern University, ECE Department, Aug. 2002.

 

31. Pramod Joisha, “A Type Inferencing System for MATLAB,” Northwestern University, ECE Department, Aug. 2003.

 

32. Xiaoyong Tang, “High-Level Synthesis Algorithms for Low Power ASIC Design,” Northwestern University, ECE Department, June 2004.

 

33. Tianyi Jiang, “Power Aware High-level Sythnesis Techniques for FPGAs,” Northwestern University, ECE Department, June 2004.

 

34. Gaurav Mittal, “A Compiler Infrastructure for Compiling Assembly and Binary Programs onto Field Programmable Gate Arrays.” Northwestern University, ECE Department, August 2004.

 

35. David Zaretsky, “A Methodology for Mapping Scheduled Software Binaries onto Field Programmable Gate Arrays.” Northwestern University, ECE Department, September 2005.

 

M.S. Theses Supervised: 40

 

A. Dugar (1986), R. M. Kling (1987), A. L. N. Reddy (1987), V. Balasubramanian (1987), M. Jones (1987), R. Brouwer (1988),A. Hagin (1988), K. P. Belkhale (1988), J. Sargent (1988), M. Peercy (1989), S. Kim (1989), H. Rao (1989), K. De (1990), G. Zipfel(1991), C. F. Lim (1991), A. Roy Chowdhury (1992), J. Chandy (1992), E. Su (1993), K. McPherson (1995), E. W. Hodges (1995), A. Mishra (1995), G. Hasteer (1995), S. Roy (1996), V. Kim (1998), P. Joisha (1998), A. Ye (1999), S. Periyacheri (1999), C. Bachmann (1999), A. Nayak (1999), M. Haldar (1999), A. Jones (2000), D. Zaretsky (2001), M. Walkden (2001), S. Pal (2001), D. Bagchi (2001), N. Tripathi (2001), N. Liveris (2003), R. Mukherjee (2003), S. Roy (2003), A. Malik (2004).

 

 

COMPANIES WHERE FORMER Ph.D. STUDENTS ARE WORKING:

 

  • R. M. Kling, Intel
  • S. Patil, went to IBM, now at Mentor Graphics
  • K. P. Belkhale, went to IBM, now at Cadence Design Systems
  • J. M. Hsu, Hewlett Packard
  • M. Gupta, IBM
  • S. Kim, went to LSI Logic, now at Synopsys
  • K. De, went to LSI Logic, now at Cadence
  • S. Parkes, started own company, Sierra Vista Research, now at IBM Almaden
  • M. Peercy, IBM
  • A. Lain, Hewlett-Packard
  • A. Roy-Choudhary, Transarc Corporation
  • S. Ramaswamy, IBM
  • D. Palermo, Hewlett Packard
  • E. Su, Intel
  • J. Holm, Intel
  • Z. Zhing, Sun
  • V. Krishnaswamy, went to Intel, now at Calytpo Design Systems
  • D. Krishnaswamy, went to Intel, now at Calytpo Design Systems
  • G. Hasteer, Cadence Design Systems
  • S. Roy, Cadence Design Systems
  • P. Prabhakaran, Compaq-Digital
  • D. Chakrabarti, Hewlett-Packard
  • Y. Yuan, Synopsys
  • M. Haldar, went to AccelChip, now at Calypto Design Systems.
  • A. Nayak, went to AccelChip, now at Atrenta, Inc.
  • P. G. Joisha, Microsoft Research
  • X. Tang, Magma Design Automation
  • T. Jiang, Marvel
  • G. Mittal, BINACHIP
  • D. Zaretksy, BINACHIP

 

UNIVERSITIES WHERE FORMER Ph.D. STUDENTS ARE WORKING:

 

  • A. L. N. Reddy, Texas A & M University, Texas.
  • R. Brouwer, Calvin College, Michigan.
  • V. Balasubramian, Xavier University, Louisiana.
  • Amitabh Mishra, Virginia Tech
  • J. Chandy, University of Connecticut
  • A. K. Jones, University of Pittsburg

 

 

Copyright © 2004 The Board of Trustees of the University of Illinois