LIST OF PUBLICATIONS

BOOKS
 
1. P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design, Prentice-Hall, Inc., Englewoods-Cliffs, NJ, 1994.

 

PATENTS

 

  1. P. Banerjee, A. Choudhary, M. Haldar, A. Nayak , “Methods and Apparatus for Automatically Generating Hardware from Algorithms Described in MATLAB.” US Patent Number 7,000,213, granted Feb. 14, 2006.

 

  1. P. Joisha, P. Banerjee, N. Shenoy, “Method for Array Shape Inferencing for a Class of Functions in MATLAB,” US Patent Number 7,086,040,  granted Aug. 1, 2006.

 

CHAPTERS IN BOOKS

 

  1. P. Banerjee, M. Jones, J. Sargent, R, Brouwer, K. P. Belkhale, and S. Patil, "Parallel Algorithms for VLSI Computer-Aided Design Toolson Hypercube Multiprocessors,"in Advances in Computer-Aided Design, Editor: I. N. Hajj, JAI Press, England, Volume 2, 1990.

 

  1. P. Banerjee, "HIPERCAD: Parallel Algorithms for High Performance VLSI CAD",in VLSI System Design, Editors: Patnaik and Singh, Tata McGraw Hill Publishing Co., New Delhi, INDIA, pp. 27-33, 1990.

 

  1. R. K. Iyer, J. H. Patel, W. K. Fuchs, P. Banerjee, R. Horst,"Hardware and Software Fault Tolerance," Encyclopedia of Microcomputers, Marcel Dekker, 1991.

 

  1. P. Banerjee,"A Survey of Parallel Algorithms for VLSI Cell Placement," Lecture Notes in Computing, Special Issue on Algorithmic Aspects of VLSI Layout, Springer Verlag, Wien, New York,January, 1993.

 

  1. D. K. Pradhan and P. Banerjee,"Fault Tolerant Multiprocessor and Distributed Systems: Principles," chapter in Fault Tolerant System Design, Editor: D. Pradhan, Prentice-Hall, Englewoods Cliffs, NJ, 1996.

 

  1. P. Banerjee, V. Balasubramanian, and A. Roy Chowdhury, "Compiler Assisted Synthesis of Algorithm Based Checking in Multiprocessors," chapter in Foundations of Ultradependable Computing, Volume III: System Implementations Editors: G. M. Koob, C. Lau, Kluwer Academic Publishers, Norwell, MA, 1994.

 

  1. D. J. Palermo, E. W. Hodges, and P. Banerjee, "Dynamic Data Partitioning for Distributed Memory Multicomputers," chapter in Languages, Compilation Techniques, and Runtime Systems for Scalable Parallel Systems (Recent Advances and Future Perspectives) Editors: S. Pande and D. P. Agarwal, Springer Verlag Publishers, 1997.

 

  1. S. Mohan, P. Mazumder, D. Krishnaswamy, P. Banerjee, and E. M. Rudnick, "Parallel Implementations," chapter in Genetic Algorithms for VLSI Design, Layout & Test Automation, Editors: P. Mazumder and E. M. Rudnick, Prentice Hall PTR, 1999.

 

  1. M. Kandemir, J. Ramanujam, A. Choudhary, and P. Banerjee, "An Iteration Space Transformation Algorithm Based on Explicit Data Layout Representation for Optimizing Locality," in Languages and Compilers for Parallel Computers, Editors: S. Chatterjee et al., Lecture Notes in Computer Science, Springer-Verlag, 1999.

 

  1. A. Jones, D. Bagchi, S. Pal, A. Choudhary, and P. Banerjee, "PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations," in Power Aware Computing, Editors: R. Melhem and Bob Graybill, Kluwer Academic Publishers, 2001.

 

ARTICLES IN JOURNALS

 

  1. P. Banerjee and J. A. Abraham,"Characterization and Testing of Physical Failures in MOS Logic Circuits,"IEEE Design and Test, Aug. 1984, pp. 76-86.

 

  1. P. Banerjee and J. A. Abraham,"A Multi-valued Algebra for Modeling Physical Failures in MOS VLSI Circuits,"IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. CAD, no. 3, Jul. 1985, pp. 312-321.

 

  1. P. Banerjee and J. A. Abraham,"Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems,"IEEE Transactions Computers, Vol. C-35, no. 4, Apr. 1986, pp. 296-306.

 

  1. J. A. Abraham, P. Banerjee, C.-Y. Chen, W. K. Fuchs, S.-Y. Kuo, and A. L. N. Reddy, "Fault tolerance techniques for systolic arrays,"IEEE Computer, Vol. 20, no. 7, Jul. 1987, pp. 65-77.

 

  1. V. Balasubramanian and P. Banerjee,"A Fault Tolerant Massively Parallel Processing Architecture,"Journal of Distributed and Parallel Computing, Aug. 1987, pp. 363-383.

 

  1. P. Banerjee,"The Cubical Ring-Connected Cycles: A Fault Tolerant Parallel Computation Network,"IEEE Trans. Computers, Vol. C-37, No. 5, May 1988, pp. 632-636.

 

  1. D. B. West and P. Banerjee,"On The Construction of Communication Networks Satisfying Bounded Fan-in of Service Ports,"IEEE Trans. Computers, Vol. C-37, No. 9, Sep. 1988, pp. 1148-1151.

 

  1. P. Banerjee and A. Dugar,"Design, Analysis, and Simulation of a Fault-Tolerant Interconnection Network supporting the Fetch-Add Primitive,"IEEE Trans. Computers, Vol C-38, No. 1, Jan. 1989, pp. 30-46.

 

  1. R. M. Kling and P. Banerjee,"ESP: Placement by Simulated Evolution,"IEEE Trans. Computer-Aided Design of Circuits and Systems, Vol. CAD-8, no. 3, Mar. 1989, pp. 245-256.

 

  1. A. L. N. Reddy and P. Banerjee,"An Evaluation of Multiple-Disk I/O Systems,"IEEE Trans. Computers, Vol. 38, no. 12, Dec. 1989, pp. 1680-1690.

 

  1. P. Banerjee, M. H. Jones, and J. S. Sargent,"Parallel Simulated Annealing Algorithms for Standard Cell Placement on Hypercube Multiprocessors,"IEEE Trans. Parallel and Distributed Systems, Vol. 1, no. 1, Jan. 1990, pp. 91-106.

 

  1. V. Balasubramanian and P. Banerjee,"Trade-offs in the Design of Efficient Algorithm-Based Error Detection Schemes for Hypercube Multiprocessors,"IEEE Trans. Software Engineering, Vol. 16, no. 2, Feb. 1990, pp. 183-195.

 

  1. S. Patil and P. Banerjee,"A Parallel Branch and Bound Algorithms for Test Generation,"IEEE Trans. Computer-Aided Design of Circuits and Systems, Vol. 9, no. 3, Mar. 1990, pp. 313-322.

 

  1. A. L. N. Reddy and P. Banerjee,"Design, Analysis and Simulation of I/O Architectures for Hypercube Multiprocessors,"IEEE Trans. Parallel and Distributed Systems, Vol. 1, no. 2, Apr. 1990, pp. 140-151.

 

  1. V. Balasubramanian and P. Banerjee,"Compiler Assisted Algorithm-Based Checking for Multiprocessors,"IEEE Trans. Computers, Apr. 1990, Vol. 39, no. 4,pp. 436-447.

 

  1. P. Banerjee, J. T. Rahmeh, C. B. Stunkel, V. S. S. Nair, K. Roy, J. A.Abraham, and V. Balasubramanian, "Algorithm Based Fault Tolerance on Hypercube Multiprocessors,"IEEE Trans. Computers, Vol. 39, No.9, pp 1132-1142, Sep. 1990.

 

  1. A. L. N. Reddy and P. Banerjee,"Algorithm-Based Fault Detection in Signal Processing Applications,"IEEE Trans. Computers, Vol. 39, No. 10, pp. 1304-1308, Oct. 1990.

 

  1. K. P. Belkhale and P. Banerjee,"Reconfiguration Strategies for VLSI Processor Arrays and Trees Using a Modified Diogenes Approach"IEEE Trans. Computers, Jan. 1992.

 

  1. K. P. Belkhale and P. Banerjee"Parallel Algorithms for VLSI Circuit Extraction"IEEE Trans. Computer Aided Design, Vol. 10, No. 5, pp. 604-618, May 1991.

 

  1. S. Patil and P. Banerjee,"Performance Trade-offs in a Parallel Test Generation Fault Simulation Environment,"IEEE Trans. Computer-Aided Design, Vol. 10, No. 12, Dec. 1991, pp. 1542-1558.

 

  1. R. M. Kling and P. Banerjee,"Empirical and Theoretical Studies of the Simulated Evolution Method Applied to Standard Cell Placement,"IEEE Trans. Computer-Aided Design, Oct. 1991, Vol. 10, no. 10, pp. 1303-1315.

 

  1. M. Gupta and P. Banerjee,"Demonstration of Automated Data Partitioning Techniques in Parallelizing Compilers for Distributed Memory Multiprocessors,"IEEE Trans. Parallel and Distributed Systems, March, 1992, Vol. 3, no. 2, pp. 179-193.

 

  1. J.-M. Hsu and P. Banerjee, "Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer,"IEEE Trans. Parallel and Distributed Systems, July 1992, Vol. 3, No. 3, pp. 451-464.

 

  1. K. P. Belkhale and P. Banerjee,"Parallel Algorithms for Geometric Connected Labeling on Hypercube Multiprocessors,"IEEE Trans. Computers, Vol. 41, No. 6, Jun. 1992, pp. 699-709.

 

  1. A. L. N. Reddy, J. Chandy, and P. Banerjee,"Design and Evaluation of Gracefully Degraded Disk Arrays,"Journal of Parallel and Distributed Computing, Jan. 1993.

 

  1. M. Peercy and P. Banerjee,"Fault Tolerant VLSI Systems,"Proceedings of the IEEE (Special Issue on VLSI Reliability), (invited paper),May 1993, Volume 81, number 5, pp. 745-758.

 

  1. K. P. Belkhale and P. Banerjee,"Task Scheduling for Exploiting Parallelism and Hierarchy in VLSI CAD Applications,"IEEE Trans. Computer-Aided Design, Volume 12, number 5, May 1993, pp. 557-567.

 

  1. K. De and P. Banerjee,"PREST: A System for Logic Partitioning and Resynthesis,"IEEE Trans. On VLSI Systems, Vol. 1, no. 4, pp. 514-525, December 1993.

 

  1. K. De, B. Ramkumar and P. Banerjee,"A Portable Parallel Algorithm for Logic Synthesis using Transduction," IEEE Trans. Computer-Aided Design, Volume 13, number 5, May 1994, pp. 566-580.

 

  1. P. Banerjee and M. Peercy, "Design and Evaluation of Hardware Reconfiguration Strategies for Hyper cubes and Meshes," IEEE Transactions on Computers, Volume 43, Number 7, July 1994, pp. 841-848.

 

  1. K. De. C. Natarajan, D. Nair, and P. Banerjee, "RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits," IEEE Transactions on VLSI Systems, Volume 2, number 2, June 1994, pp. 186-195.

 

  1. B. Ramkumar and P. Banerjee, "ProperCAD: A Portable Object Oriented Parallel Environment for VLSI CAD," IEEE Transactions on Computer-Aided Design, Volume 13, Number 7, July 1994, pp. 829-842.

 

  1. M. Gupta and P. Banerjee, "Compile-time Estimation of Communication Costs of Programs," Jour. Programming Languages, Vol. 2 (1994), pp. 191-225.

 

  1. P. Banerjee, J. Chandy, M. Gupta, J. G. Holm, A. Lain, D. J. Palermo, S. Ramaswamy and E. Su, "The PARADIGM Compiler for Distributed Memory Multicomputers," IEEE Computer, Vol. 28, No. 10, Oct. 1995, pp. 37-47.

 

  1. S. Ramaswamy and P. Banerjee, "Simultaneous Allocation and Scheduling Using Convex Programming Techniques," Parallel Processing Letters (Special Issue on Partitioning and Scheduling), Dec. 1995.

 

  1. A. Roy-Chowdhury and P. Banerjee, "A New Error Analysis Based Method for Tolerance Computation for Algorithm-Based Checks," IEEE Trans. Computers, Vol. 45, No. 2, Feb. 1996, pp. 238-243.

 

  1. V. S. S. Nair, J. A. Abraham, P. Banerjee, "Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes" IEEE Trans. Computers, Vol. 45, No. 4, Apr. 1996, pp. 499-502.

 

  1. A. Roy Chowdhury, N. Bellas, and P. Banerjee, "Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations," IEEE Trans. Computers, Vol. 45, No. 4, Apr 1996, pp 394-407.

 

  1. A. Roy-Chowdhury and P. Banerjee, "Algorithm-based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems," IEEE Trans. Computers, Vol. 45, no. 11, Nov. 1996, pp. 1239-1247.

 

  1. E. Rudnick, V. Chickermane, P. Banerjee, J. H. Patel, "Sequential Circuit Testability Enhancement Using a Non-scan Approach," IEEE Transactions on VLSI Systems, 1996.

 

  1. K. McPherson and P. Banerjee, "Parallel Algorithms for VLSI Layout Verification," Journal of Parallel and Distributed Computing, Vol. 36, No. 2, August 1996, pp. 156-172.

 

  1. D. Palermo, E. W. Hodges and P. Banerjee, "Dynamic Data Partitioning for Distributed Memory Multicomputers," Journal of Parallel and Distributed Computing (Special Issue on Compilation Techniques for Distributed Memory Systems) November 1, 1996, Vol. 38, no. 2, pp. 158-175.

 

  1. S. Ramaswamy, B. Simons and P. Banerjee, "Optimizations for Efficient Array Redistribution on Distributed Memory Multicomputers," Journal of Parallel and Distributed Computing (Special Issue on Compilation Techniques for Distributed Memory Systems) November 1, 1996, Vol. 38, no. 2, pp. 217- 228.

 

  1. S. Ramaswamy, S. Sapatnekar, and P. Banerjee, "A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers," IEEE Trans. Parallel and Distributed Systems, Vol. 8, No. 11, pp. 1098-1116, November 1997.

 

  1. B. Ramkumar and P. Banerjee, "ProperTEST: A Portable Parallel Test Generator for Sequential Circuits," IEEE Trans. Computer-Aided Design, Vol. 16, No. 5, pp. 555-569, May 1997.

 

  1. G. Hasteer and P. Banerjee, "A Parallel Algorithm for State Assignment of Finite State Machines," IEEE Transactions on Computers, Vol. 47, No. 2, February 1998, pp. 242-246.

 

  1. V. Krishnaswamy, R. Gupta and P. Banerjee, "Implications of VHDL Timing Models on Simulation and Software Synthesis," Journal of Systems Architecture, North-Holland Elsevier Publishers, Vol. 44, 1997, pp. 23-36.

 

  1. G. Hasteer and P. Banerjee, "Simulated Annealing Based Parallel State Assignment for Finite State Machines," Journal of Parallel and Dist. Computing, Vol. 43, no. 1, May 25, 1997, pp. 21-35.

 

  1. J. A. Chandy, S. Kim, B. Ramkumar, S. Parkes, and P. Banerjee "An Evaluation of Parallel Simulated Annealing Strategies with Applications to Standard Cell Placement", IEEE Trans. on Computer Aided Design, Vol. 16, No. 4, pp. 398-410, April 1997.

 

  1. G. Hasteer, A. Mathur, and P. Banerjee, "Efficient Equivalence Checking of Multi-Phase Designs Using Phase Abstraction and Retiming.," ACM Transactions on Design Automation of Electronic Systems (TODAES) Special Issue on High Level Design, Validation and Testing, Oct. 1998, pp. 600-625.

 

  1. M. Kandemir, A. Choudhary, N. Shenoy, P. Banerjee, J. Ramanujam, "A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts," IEEE Transactions on Parallel and Distributed Systems, Vol. 10, No. 2, February 1999, pp. 115-135.

 

  1. J. Chandy and P. Banerjee, "A Parallel Circuit Partitioned Algorithm for Timing-Driven Standard Cell Placement," Journal of Parallel and Distributed Computing, vol. 57., No. 1, pp. 64-90, April 1999.

 

  1. P. Prabhakaran and P. Banerjee, "Parallel Algorithms for Force-Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs," IEEE Transactions on Computers, 1999.

 

  1. M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and N. Shenoy, "A Global Communication Optimization Technique Based on Data Flow Analysis and Linear Algebra," ACM Trans. on Programming Languages and Systems (TOPLAS), Vol. 21, No. 6, Nov. 1999.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "A Matrix-Based Approach to Global Locality Optimization," Journal of Parallel and Distributed Computing, Special Issue on Compilation and Architectural Support for Parallel Applications, Vol. 58, No. 2, Aug. 1999, pp. 190-235.

 

  1. A. Lain, D. Chakrabarti, and P. Banerjee, "Compiler and Run-Time Support for Exploiting Regularity Within Irregular Applications," IEEE Transactions on Parallel and Distributed Systems (IEEE TPDS), Vol. 11, No. 2, February 2000.

 

  1. M. Kandemir, N. Shenoy, P. Banerjee, J. Ramanujam, and A. Choudhary, "Minimizing Data and Synchronization Costs in One-Way Communication," IEEE Transactions on Parallel and Distributed Systems, Vol. 11, No. 12, December 2000, pp. 1232-1251.

 

  1. N. Shenoy, A. Choudhary, and P. Banerjee, "An Algorithm for Synthesis of Large Time-constrained Heterogeneous Adaptive Systems," ACM Transactions on the Design Automation of Electronic Systems, Vol. 6, No. 2, April 2001.

 

  1. D. R. Chakrabarti and P. Banerjee, "Static Single Assignment Form for Message-Passing Programs," International Journal of Parallel Programming, to appear, 2001.

 

  1. A. Nayak, M. Haldar, C. Chen, M. Sarrafzadeh, P. Banerjee, "Power Optimizations in Delay Constrained Circuits" VLSI Design Journal to appear, 2001.

 

  1. P. Joisha and P. Banerjee, "The Efficient Computation of Ownership Sets in HPF," IEEE Transactions on Parallel and Distributed Systems, Vol. 12, No. 8, August 2001.

 

  1. M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and E. Ayguade, "Static and Dynamic Locality Optimizations Using Integer Linear Programming," IEEE Transactions on Parallel and Distributed Systems, Vol. 12, No. 9, pp. 922-941, September 2001.

 

  1. Y. Yuan and P. Banerjee, "A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers," Journal of Parallel and Distributed Computing, Vol. 61, No. 12, December 2001, pp. 1751-1774.

 

  1. V. Kim, P. Banerjee, K. De, and J. Brouwers, "Parallel and Distributed VLSI Synthesis on a Network of Workstations," International Journal of Parallel and Distributed Systems and Networks. to appear, 2001.

 

  1. M. Kandemir, A. Choudhary, P. Banerjee, and J. Ramanujam, "Reducing False Sharing and Improving Spatial Locality in a Unified Compilation Framework," IEEE Transactions on Parallel and Distributed Systems, to appear.

 

  1. M. Kandemir, J. Ramanujam, A. Choudhary, and P. Banerjee, "A Layout-Conscious Iteration Space Transformation Technique," IEEE Transactions on Computers, Vol. 50, No. 12, December 2001, pp. 1321-1336.

 

  1. V. Krishnaswamy, G. Hasteer and P. Banerjee, "Automated Parallelization of Compiled Event Driven VHDL Simulation," IEEE Transactions on Computers, Vol. 51, No. 4, April 2002, pp. 380-394.

 

  1. A. Mishra and P. Banerjee, "An Algorithm Based Error Detection Scheme for the Multigrid Method," IEEE Transactions on Computers, Vol. 52, No. 9, Sep. 2003, pp. 1089-1099.

 

  1. P. Banerjee, V. Saxena, J. Uribe, M. Haldar, A. Nayak, V. Kim, S. Parkes, D. Bagchi, S. Pal, D. Zaretsky, N. Tripathi, B. Jiang, R. Anderson, T. Vanevenhoven, D. Nandy, "Overview of a Compiler for Synthesizing MATLAB Programs onto FPGAs,"  IEEE Transactions on VLSI Systems, Vol. 12, No. 4, April 2004.

 

  1. T. Jiang, X. Tang, P. Banerjee, “Macro-models for high-level area and power estimation on FPGAs,” to appear in special issue on Mathematical Modeling and Simulation for Industrial Applications of the International Journal of Simulation and Process Modeling, June 2005.

 

  1. S. Roy and P. Banerjee, "An Algorithm for Trading off Quantization Error with Hardware Resources for MATLAB based FPGA Design,” IEEE Transactions on Computers, July 2005, Vol. 54, No. 7, pp. 886-896.

 

  1. P. Joisha and P. Banerjee, “An Algebraic Type Inference System for MATLAB“, ACM Transactions on Programming Languages and Systems (TOPLAS), to appear, 2006.

 

  1. X. Tang, T. Jiang, A. K. Jones, and P. Banerjee, “High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits,” Journal of Low Power Electronic (JOLE), American Scientific Publishers, to appear, 2006.

 

  1. P. Joisha and P. Banerjee, “A Translator System for the MATLAB Language,” Software Practices and Experiences, to appear, 2006

 

  1. A. Mallik, D. Sinha, H. Zhou, and P. Banerjee, “Low Power Optimization by Smart Bit-width Allocation in a SystemC based ASIC Design Environment”, IEEE Transactions on Computer Aided Design of Integrated Circuits, to appear, 2006.

 

PUBLICATIONS IN CONFERENCE PROCEEDINGS

 

  1. P. Banerjee and J. A. Abraham, "Fault Characterization of VLSI MOS Circuits,"Proceedings, Interna tional Conference on Circuits and Computers, New York, NY, Sep. 1982, pp. 564-568.

 

  1. P. Banerjee and J. A. Abraham,"MURPHY: A Logic Simulator for nMOS and CMOS VLSI Circuits,"Proceedings, International Conference on Computer-Aided Design, Santa Clara, CA, Sep. 1983, pp. 94-95.

 

  1. P. Banerjee and J. A. Abraham,"Generating Tests for Physical Failures in MOS Logic Circuits,"Proceedings, International Test Conference, Cherry Hill, Philadelphia, Oct. 1983, pp. 554-559.

 

  1. P. Banerjee and J. A. Abraham,"Fault-Secure Algorithms for Multiple-Processor Systems,"Proceedings, 11th Annual International Symp. on Computer Architecture, Ann Arbor, MI, Jun. 1984, pp. 279-287.

 

  1. D. B. West and P. Banerjee,"Partial Matching in Degree-Restricted Bipartite Graphs,"Proc., Southeastern Intl. Conf. on Combinatorics, Graph Theory, and Computing, Congressus Numeratium, Boca Raton, FL, Feb. 1985, vol. 49, pp. 259-266.

 

  1. P. Banerjee and J. A. Abraham,"Graph-Theoretic Bounds for On-Line Checks in Multiple Processor Systems,"Proceedings, AFIPS National Computer Conference, Las Vegas, NV, vol. 55, Jun. 1986, pp. 283-296.

 

  1. P. Banerjee, S. Y. Kuo, and W. K. Fuchs,"Reconfigurable Cube-Connected Cycles Architectures,"Proceedings, 16th Annual Symposium on Fault-Tolerant Computing, Vienna, Austria, Jul. 1986, pp. 286-291.

 

  1. P. Banerjee and J. A. Abraham,"Concurrent Fault Diagnosis in Multiple Processor Systems,"Proceedings 16th Annual Symposium on Fault-Tolerant Computing, Vienna, Austria, Jul. 1986, pp. 298-303.

 

  1. A. Dugar and P. Banerjee,"A Fault-Tolerant Interconnection Network Supporting the Fetch-Add Primitive,"Proceedings, International Conference on Parallel Processing, St. Charles, IL, Aug. 1986, pp. 327-334.

 

  1. V. Balasubramanian and P. Banerjee,"RECBAR: A Reconfigurable Massively Parallel Processing Architecture,"Proceedings, International Conference on Parallel Processing, St. Charles, IL, Aug. 1986, pp. 390-393.

 

  1. R. M. Kling and P. Banerjee,"A Novel Circuit Design Providing Concurrent Error Detection in PLAs,"Proceedings, International Conference on Computer Design: VLSI in Computers, New York, NY, Oct. 1986, pp. 588- 591.

 

  1. P. Banerjee and M. Jones,"A Parallel Simulated Annealing Algorithm for Standard Cell Placement on a Hypercube Computer,"Proceedings, International Conference on Computer-Aided Design, Santa Clara, CA, Nov. 1986, pp. 34-37.

 

  1. P. Banerjee and J. A. Abraham,"A Probabilistic Model of Algorithm-Based Fault Detection and Tolerance in Array Processors for Real-Time Systems,"Proceedings, Real-Time Systems Symposium, New Orleans, LA, Dec. 1986, pp. 72-78.

 

  1. A. L. N. Reddy and P. Banerjee,"A Fault-Secure Dictionary Machine,"Proceedings, Third International Conference on Data Engineering, Los Angeles, CA, Feb. 1987, pp. 104-109.

 

  1. R. M. Kling and P. Banerjee, "ESP: A New Standard Cell Placement Package Using Simulated Evolution,"Proceedings, 24th Design Automation Conference, Miami Beach, FL, Jun. 1987, pp. 60-66.

 

  1. M. Jones and P. Banerjee, "Performance of a Parallel Algorithm For Standard Cell Placement On The Intel Hypercube,"Proc. 24th Design Automation Conf., Miami Beach, FL, Jun. 1987, pp. 807-813.

 

  1. B. Cunningham, W. K. Fuchs and P. Banerjee,"Fault Characterization and Delay Fault Testing of GaAs Logic Circuits,"Proc. Int. Test Conf., Washington, DC, Sep. 1987, pp. 836-842.

 

  1. M. Jones and P. Banerjee,"An Improved Simulated Annealing Algorithm for Standard Cell Placement,"Proc. Int. Conf. on Computer Design, New York, NY, Oct. 1987, pp. 83-87.

 

  1. R. M. Kling and P. Banerjee,"Concurrent ESP: A Placement Algorithm for Executive on Distributed Processors,"Proc. Int. Conf. on Computer-Aided Design (ICCAD-87), Santa Clara, CA, Nov. 1987, pp. 354-357.

 

  1. V. Balasubramanian and P. Banerjee,"A Fixed Size Array Processor for Computing the Fast Fourier Transform," Proc. 8th IEEE Real-Time Systems Symp., San Jose, CA, Dec. 1987, pp. 36-43.

 

  1. P. Banerjee,"Parallel Algorithms For VLSI CAD Tools on Hypercube Multiprocessors,"Proc. Int. Symp. on Electronic Devices, Circuits and Systems, Kharagpur, India, pp. 677-679, Dec. 1987.

 

  1. P. Banerjee and C. Stunkel,"A Novel Approach to System-Level Fault Tolerance in Hypercube Multiprocessors," Proc. 3rd ACM Conference on Hypercube Concurrent Computers and Applications, Pasadena, CA, Jan. 1988, pp. 307-311.

 

  1. P. Banerjee, J. T. Rahmeh, C. Stunkel, V. S. S. Nair, K. Roy, and J. A. Abraham,"An Evaluation of System-level Fault Tolerance on the Intel Hypercube Multiprocessor,"Proc. 18th Int. Symp. Fault Tolerant Computing, Tokyo, Japan, 362-367, Jun. 1988.

 

  1. A. L. N. Reddy, P. Banerjee, and S. G. Abraham,"I/O Embedding in Hypercubes,"Proc. 17th Int. Conf. on Parallel Processing, Aug. 1988, St. Charles, IL, pp. 331-338.

 

  1. R. Brouwer and P. Banerjee,"A Parallel Simulated Annealing Algorithm for Channel Routing on a Hypercube Multiprocessor,"Proc. Int. Conf. on Computer-Design (ICCD-88), Oct. 1988, Rye Brook, NY, pp. 4-7.

 

  1. K. P. Belkhale and P. Banerjee,"Reconfiguration Strategies in VLSI Processor Arrays,"Proc. Int. Conf. on Computer-Design (ICCD-88), Oct. 1988, Rye Brook, NY, pp. 418-421.

 

  1. K. P. Belkhale and P. Banerjee,"PACE: A Parallel VLSI Circuit Extractor on the Intel Hypercube Multiprocessor,"Proc. Int. Conf. on Computer-Aided Design, Santa Clara, CA, Nov. 1988, pp. 326-329.

 

  1. P. Banerjee, "Reconfiguring a Hypercube Multiprocessor in the Presence of Faults,"Proc. 4th ACM Conf. on Hypercube Concurrent Computers and Applications, Monterey, CA, Mar. 1989.

 

  1. R. Kling and P. Banerjee,"A Special Purpose Coprocessor for Supporting Cell Placement and Floorplanning Algorithms,"Proc. Custom Integrated Circuits Conf., San Diego, CA, May 1989.

 

  1. A. L. N. Reddy and P. Banerjee,"I/O Issues for Hypercubes,"Proc. 3rd Int. Conf. on Supercomputing, Athens, Greece, Jun. 1989.

 

  1. S. Patil and P. Banerjee,"A Parallel Branch and Bound Algorithms for Test Generation,"Proc. 26th Design Automation Conf., Las Vegas, NV, Jun. 1989, pp. 339-345.

 

  1. J. Sargent and P. Banerjee,"A Parallel Row-Based Algorithm for Standard Cell Placement with Integrated Error Control,"Proc. 26th Design Automation Conf., Las Vegas, NV, Jun. 1989,pp. 590-594.

 

  1. R. B. Mueller-Thuns,D. McFarland and P. Banerjee,"Algorithm-Based Fault Tolerance for Adaptive Least Squares Lattice Filtering on a Hypercube Multiprocessor,"Proc. Int. Conf. on Parallel Processing, St. Charles, IL, Aug. 1989, pp. 177-183.

 

  1. A. L. N. Reddy and P. Banerjee,"Performance Evaluation of Multiple-Disk I/O Systems,"Proc. Int. Conf. on Parallel Processing, St. Charles, IL, Aug. 1989, pp.315-319.

 

  1. S. Patil and P. Banerjee,"Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment,"Proc. Int. Test Conf., Washington, DC, Sep. 1989, pp. 718-727.

 

  1. S. Kim and P. Banerjee,"An Accurate Timing Model for Fault Simulation in MOS Circuits,"Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA,Nov. 1989, pp.76-79.

 

  1. K. P. Belkhale and P. Banerjee,"PACE2: An Improved Parallel VLSI Extractor with Parametric Extraction,"Proc. Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 1989, pp. 526-529.

 

  1. S. Patil, P. Banerjee, and C. Polychronopolous,"Efficient Circuit Partitioning Algorithms for Parallel Logic Simulation,"Proc. Supercomputing Conf., Reno, NV, Nov. 89, pp. 361-364.

 

  1. V. Balasubramanian and P. Banerjee,"Algorithm based Error Detection for Signal Processing Application on a Hypercube Multiprocessor,"Proc. 10th Int. Real-time Systems Symp., Los Angeles, CA, Dec. 1989.

 

  1. K. P. Belkhale and P. Banerjee,"Recursive Partitions on Multiprocessors",Proc. 5th Distributed Memory Computing Conference, Charleston, SC, Apr. 1990.

 

  1. M. Peercy and P. Banerjee,"A Method for Evaluating Message Communication in Faulty Hypercubes,"Proc. 5th Distributed Memory Computing Conference,Charleston, South Carolina, Apr. 1990.

 

  1. J.-M. Hsu and P. Banerjee, "Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube Multicomputer, "Proc. 17th Int. Symp. Computer Architecture, Seattle, WA, May, 1990, pp. 260-269.

 

  1. A.L.N. Reddy and P Banerjee,"A Study of I/O Behavior of Perfect Benchmarks on a Multiprocessor,"Proc. 17th Int. Symp. Computer Architecture, Seattle, WA, May, 1990, pp. 312-321.

 

  1. R. J. Brouwer and P. Banerjee,"PHIGURE: A Parallel Hierarchical Global Router",Proc. 27th ACM/IEEE Design Automation Conf., Orlando, FL, Jun. 1990, pp. 360-364.

 

  1. R-M. Kling and P. Banerjee,"Optimization by Simulated Evolution with Application to Standard Cell Placement",Proc. 27th ACM/IEEE Design Automation Conf., Orlando, FL, Jun. 1990, pp. 20-25.

 

  1. M. Peercy and P. Banerjee"Distributed Algorithms for Shortest-Path, Deadlock-Free Routing and Broadcasting in Arbitrarily Faulty Hypercubes"Proc. 20th Int. Symp. on Fault-Tolerant Computing (FTCS20), Newcastle, England, Jun. 1990, pp. 218-225.

 

  1. P. Banerjee,"Strategies for Reconfiguring Hypercubes Under Faults"Proc. 20th Int. Symp. on Fault Tolerant Computing (FTCS-20), Newcastle, England, Jun. 1990, pp. 210-215.

 

  1. K. P. Belkhale and P. Banerjee, "Geometric Connected Component Labeling on Distributed Memory Multiprocessors,"Proc. of Int. Conf. on Parallel Processing, St. Charles, IL, Aug. 1990, Vol. III, pp. 291-295.

 

  1. J-M. Hsu and P. Banerjee"Hardware Support for Message Routing in a Distributed Memory Multicomputer"Proc. of Int. Conf. on Parallel Processing, St. Charles, IL, Aug. 1990, vol. I, pp. 508-515.

 

  1. K. Belkhale and P. Banerjee, "Approximate Algorithms for the Partitionable Independent Task Scheduling Problem"Proc. of Int. Conf. on Parallel Processing, St. Charles, IL, Aug. 1990, Vol. I, pp. 72-75.

 

  1. D. T. Blaauw, P. Banerjee, and J. A. Abraham, "Automatic Classification of Node Types in Switch-Level Descriptions,"Proc. Int. Conf. on Computer Design (ICCD-90), Oct. 1990, Boston, MA.

 

  1. D. T. Blaauw, R. B. Mueller-Thuns, D. G. Saab, P. Banerjee, and J. A. Abraham, "SNEL: A Switch level Simulator Using Multiple Levels of Functional Abstraction", Proc. Int. Conf. Compt. Aided Design (ICCAD-90), Nov. 1990, Santa Clara, CA.

 

  1. K. P. Belkhale and P. Banerjee, "A Parallel Algorithm for Hierarchical Circuit Extraction"Proc. Int. Conf. Compt. Aided Design (ICCAD-90), Nov. 1990, Santa Clara, CA.

 

  1. J. M. Hsu and P. Banerjee,"A Message Passing Coprocessor for Distributed Memory Multicomputers," Proc. ACM Supercomputing Conf., Nov. 1990, New York, NY.

 

  1. K. De and P. Banerjee,"Can Test Length Be Reduced During Synthesis Process?,"Int. VLSI Design Conf. (VLSI-91), New Delhi, India, Jan. 1991.

 

  1. D. Blaauw, D. Saab, P. Banerjee, and J. A. Abraham, "Functional Abstraction of Logic Gates for Switch Level Simulation,"Proc. European Design Automation Conf. (EDAC-91), Amsterdam, Netherlands, Mar. 1991.

 

  1. K. P. Belkhale and P. Banerjee, "A Scheduling Algorithm for Parallelizable Dependent Tasks," Proc. 5th Int. Parallel Processing Symp. (IPPS-5), Los Angeles, CA, Apr. 1991.

 

  1. M. Gupta and P. Banerjee,"Automated Data Partitioning on Distributed Memory Multiprocessors,"Proc. 6th Distributed Memory Multicomputers Conference (DMMC6), Portland, OR, May 1991.

 

  1. S. Patil and P. Banerjee,"Parallel Test Generation for Sequential Circuits on General Purpose Multiprocessors,"Proc. 28th Design Automation Conf. (DAC-91), San Francisco, CA, Jun. 1991.

 

  1. A. L. N. Reddy and P. Banerjee,"Gracefully Degradable Disk Arrays,"Proc. 21st Fault Tolerant Computing Symp. (FTCS-21), Montreal, CANADA, Jul. 1991.

 

  1. J. M. Hsu and P. Banerjee,"Performance Evaluation of Hardware Support for Message Passing in Distributed Memory Multicomputers,"Proc. Int. Conf. Parallel Processing (ICPP-91), St. Charles, IL, Aug. 1991.

 

  1. V. Balasubramanian and P. Banerjee,"CRAFT: Compiler-Assisted Algorithm-Based Fault Tolerance in Distributed Memory Multiprocessors,"Proc. Int. Conf. Parallel Processing (ICPP-91), St. Charles, IL, Aug. 1991.

 

  1. A. L. N. Reddy, P. Banerjee and D. K. Chen,"Compiler Support for Parallel I/O Operations,"Proc. Int. Conf. Parallel Processing (ICPP-91), St. Charles, IL, Aug. 1991.

 

  1. S. Kim, S. Patil and P. Banerjee,"A Layout Driven Design for Testability Technique for MOS VLSI Circuits,"Proc. Int. Test Conf., Nashville, TN, Oct. 1991.

 

  1. K. De and P. Banerjee,"Logic Partitioning and Resynthesis for Testability,"Proc. Int. Test Conf., Nashville, TN, Oct. 1991.

 

  1. R. Brouwer and P. Banerjee,"PARAGRAPH: A Parallel Algorithm for Simultaneous Placement and Routing Using Hierarchy,"Proc. European Design Automation Conf. (EDAC-92), Brussels, Belgium, Mar. 1992.

 

  1. M. Gupta and P. Banerjee,"Compile-Time Estimation of Communication Costs in Multicomputers,,"Proc. Int. Parallel Proc. Symp., Beverly Hills, CA, Mar. 1992.

 

  1. K. De, C. Wu, and P. Banerjee,"Reliability Driven Logic Synthesis,"Proc. Int. Conf. Circuits and Systems (ISCAS-92), San Diego, CA, May 1992.

 

  1. S. Kim, P. Banerjee, C. Vivekanand, J. Patel,"APT: An Area-Performance-Testability Driven Placement Algorithm,"Proc. 29th Design Automation Conf., Anaheim, CA., Jun. 1992.

 

  1. M. Gupta and P. Banerjee,"A Methodology for High-Level Synthesis of Communication on Multicomputers,"Proc. 6th ACM Int. Conf. Supercomputing (ICS-92), Jul. 1992,Washington, DC.

 

  1. M. Peercy and P. Banerjee,"Design and Analysis of Software Reconfiguration Strategies of Hypercube Multiprocessors Under Multiple Faults,"Proc. 22nd Fault Tolerant Computing Symp., Jul. 1992, Boston, MA.

 

  1. B. Ramkumar and P. Banerjee,"ProperCAD: A Portable Object-Oriented Parallel Environment for VLSI CAD,"Proc. Int. Conf. on Computer Design (ICCD-92), Boston, MA, Oct. 1992.

 

  1. B. Ramkumar and P. Banerjee,"Portable Parallel Test Generation for Sequential Circuits," Proc. Int. Conf. on Computer-Aided Design (ICCAD-92), Santa Clara, CA, Nov. 1992.

 

  1. K. De, B. Ramkumar and P. Banerjee,"ProperSYN: A Portable Parallel Algorithm for Logic Synthesis,"Proc. Int. Conf. on Computer-Aided Design (ICCAD-92), Santa Clara, CA, Nov. 1992.

 

  1. J. G. Holm and P. Banerjee,"Low Cost Concurrent Error Detection in a VLIW Architecture Using Replicated Instructions,"Proc. Int. Conf. Parallel Processing (ICPP-92), St. Charles, IL, Aug. 1992, Volume I, pp. 192-195.

 

  1. C. F. Lim, P. Banerjee, K. De, and S. Muroga,"A Shared Memory Parallel Algorithm for Logic Synthesis,"Proc. 6th Int. Conf. VLSI Design, Bombay, INDIA, Jan. 1993.

 

  1. B. Ramkumar and P. Banerjee,"A Portable Parallel Algorithm for VLSI Circuit Extraction",Proc. Int. Parallel Processing Symp. (IPPS-93), Newport Beach, CA, Apr. 1993.

 

  1. V. Chickermane, E. Rudnik, P. Banerjee, and J. Patel,"Nonscan Design for Testability Techniques for Sequential Circuits,"Proc. Design Automation Conf. (DAC-93), Dallas, TX, Jun. 1993.

 

  1. A. Roy Chowdhury and P. Banerjee,"Tolerance Determination for Algorithm-based Checks Using Simplified Error Analysis,"Proc. Fault-Tolerant Computing Symposium (FTCS-93), Toulouse, FRANCE, Jun. 1993.

 

  1. M. Gupta and P. Banerjee,"PARADIGM: A Compiler for Automated Data Partitioning",Proc. Int. Conf. Supercomputing (ICS-93), Tokyo, JAPAN, Jul. 1993.

 

  1. S. Ramaswamy and P. Banerjee,"Processor Allocation and Scheduling of Macro Dataflow Graphs on Distributed Memory Multicomputers by the PARADIGM Compiler",Proc. Int. Conf. Parallel Processing (ICPP-93), St. Charles, IL, Aug. 1993.

 

  1. J. Chandy and P. Banerjee,"Reliability Evaluation of Disk Array Architectures,"Proc. Int. Conf. Parallel Processing (ICPP-93), St. Charles, IL, Aug. 1993.

 

  1. A.  Roy Chowdhury and P. Banerjee,"A Fault Tolerant Parallel Algorithm for Iterative Solution of the Laplace Equation," Proc. Int. Conf. Parallel Processing (ICPP-93), St. Charles, IL, Aug. 1993.

 

  1. E. Su, D. Palermo, and P. Banerjee,"Automatic Parallelization of Regular Computations for Distributed Memory Multicomputers in the PARADIGM Compiler," Proc. Int. Conf. Parallel Processing (ICPP-93), St. Charles, IL, Aug. 1993.

 

  1. S. Kim, J. Chandy, B. Ramkumar, S. Parkes, and P. Banerjee, "ProperPLACE: A Portable, Parallel Algorithm for Standard Cell Placement," Proc. 8th Int. Parallel Processing Symp., Cancun, Mexico, April 1994, pp. 932-941.

 

  1. J. Holm, A. Lain, and P. Banerjee, "Compilation of Scientific Programs into Multithreaded and Message Driven Computation," Proc. Scalable High Performance Computing Conf., Knoxville, TN, May 1994, pp. 519-524.

 

  1. S. Parkes, P. Banerjee, and J. Patel, "ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test Generation", Proc. 31st Design Automation Conf., San Diego, CA, June 1994, pp. 717-721.

 

  1. A. Roy Chowdhury and P. Banerjee, "Algorithm-based Fault Location and Recovery for Matrix Computations," Proc. Fault Tolerant Computing Symp., Austin, TX, July 1994, pp. 38-48.

 

  1. T. Karnik, S. Ramaswamy, S. M. Kang, and P. Banerjee, "Application of Algorithm Based Fault Tolerance Techniques to High Level Synthesis of Signal Flow Graphs," Proc. SPIE Int. Symp. Advanced Signal Processing Algorithms Architectures Implementations V, San Diego, CA, July 1994, pp. 760-776.

 

  1. A. Lain and P. Banerjee, "Techniques to Overlap Computation and Communication in Irregular Iterative Applications," Proc. Int. Conf. Supercomputing, Manchester, England, July 1994, pp. 236-245.

 

  1. E. Su, D. Palermo, and P. Banerjee, "Processor Tagged Descriptors: A Data Structure for Compiling for Distributed Memory Multicomputers," Proc. Conf. Parallel Architectures Compilation Techniques, Montreal, Canada, Aug. 1994, pp. 123-134.

 

  1. D. Palermo, E. Su, and P. Banerjee, "Communication Optimizations Used in the PARADIGM Compiler for Distributed Memory Multicomputers," Proc. Int. Conf. Parallel Processing, St. Charles, IL, Aug. 1994,Vol II-1-11. THIS PAPER RECEIVED THE OUTSTANDING PAPER AWARD AT ICPP-94.

 

  1. K. De and P. Banerjee, "Parallel Logic Synthesis Using Partitioning," Proc. Int. Conf. Parallel Processing, St. Charles, IL, Aug. 1994, Vol. III-135-141.

 

  1. S. Ramaswamy, S. Sapatnekar, and P. Banerjee, "A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers," Proc. Int. Conf. Parallel Processing, St. Charles, IL, Aug. 1994, Vol. II-116-125.

 

  1. S. Parkes, J. Chandy, and P. Banerjee, "A Library-Based Approach to Portable, Parallel, Object-Oriented Programming: Interface, Implementation, and Application," Proc. ACM Supercomputing 94 Conf., Washington, DC, Nov. 1994, pp. 69-78.

 

  1. P. Banerjee, J. Chandy, M. Gupta, J. G. Holm, A. Lain, D. J. Palermo, S. Ramaswamy and E. Su, "The PARADIGM Compiler for Distributed Memory Message-Passing Multicomputers," Proc. First Int. Workshop on Parallel Processing, Bangalore, INDIA, Dec. 1994, pp. 322-330.

 

  1. P. Banerjee, "A Survey of Current and Future Research Directions in Parallel CAD", Proc. Parallel and Distributed LSI-CAD Workshop, Tokyo, JAPAN, Dec. 1994, pp. 57-66.

 

  1. S. Ramaswamy and P. Banerjee, "Automatic Generation of Efficient Array Redistribution Routines for Distributed Memory Multicomputers," Proc. 5th Symp. Frontiers of Massively Parallel Computation', McLean, VA, Feb. 1995, pp. 342-349.

 

  1. A. Lain and P. Banerjee, "Exploiting Spatial Regularity with Irregular Iterative Applications," Proc. 8th Int. Parallel Processing Symp (IPPS-95), Santa Barbara, CA, Apr. 1995.

 

  1. K. De, J. Chandy, S. Roy, S. Parkes and P. Banerjee, "Parallel Algorithms for Logic Synthesis Based on MIS" Proc. 8th Int. Parallel Processing Symp (IPPS-95), Santa Barbara, CA, Apr. 1995.

 

  1. M. Peercy and P. Banerjee, "Software Schemes of Reconfiguration and Recovery in Distributed Memory Multicomputers Using the Actor Model" Proc. Fault Tolerant Computing Symp. (FTCS-25), Jun. 1995, Pasadena, CA.

 

  1. D. Palermo and P. Banerjee, "Automatic Selection of Dynamic Data Partitioning Schemes for Distributed Memory Multicomputers," Proc. 8th Int. Workshop on Languages and Compilers for Parallel Computing (LCPC95, Aug. 1995, Columbus, OH.

 

  1. S. Parkes, P. Banerjee and J. H. Patel, "A Parallel Algorithm for Fault Simulation Based on PROOFS," Int. Conf. Computer Design (ICCD 95), Austin, TX, Oct. 1995.

 

  1. J. Chandy and P. Banerjee, "Parallel Simulated Annealing Strategies for VLSI Cell Placement", 9th Int. Conf. VLSI Design, New Delhi, India, Jan. 1996.

 

  1. S. Ramaswamy, E. W. Hodges, and P. Banerjee, "Compiling MATLAB Programs to SCALAPACK: Exploiting Task and Data Parallelism," Proc. Int. Parallel Processing Symp. (IPPS-96), Honolulu, Hawaii, Apr. 1996, pp. 613-620.

 

  1. Z. Xing and P. Banerjee, "A Parallel Hierarchical Algorithm for Module Placement Based on Sparse Linear Equations", Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-96), Atlanta, GA, May 1996, Vol. IV, pp. 691-694.

 

  1. V. Krishnaswamy and P. Banerjee, "Actor-based Parallel VHDL Simulation Using Time Warp," Proc. 1996 Int. Workshop on Parallel and Distributed Simulation (PADS-96), Philadelphia, PA, May, 1996.

 

  1. A. Lain and P. Banerjee, "Compiler Support for Hybrid Irregular Accesses on Multicomputers" Proc. ACM Int. Conf. Supercomputing (ICS-96), Philadelphia, PA, May, 1996, pp. 1-9.

 

  1. A. Roy-Chowdhury and P. Banerjee, "Compiler-Assisted Generation of Error-Detecting Parallel Programs," Proc. 26th Int. Symp. on Fault-Tolerant Computing (FTCS-26), Sendai, JAPAN, Jun. 1996.

 

  1. D. Palermo, E. Su, E. W. Hodges, and P. Banerjee, "Compiler Support for Privatization for Distributed Memory Machines," Proc. Int. Conf. Parallel Processing (ICPP-96), Bloomingdale, IL, Aug. 1996.

 

  1. G. Hasteer and P. Banerjee, "A Parallel Algorithm for State Assignment in Finite State Machines," Proc. Int. Conf. Parallel Processing (ICPP-96), Bloomingdale, IL, Aug. 1996.

 

  1. V. Boppana, P. Saxena, P. Banerjee, W. K. Fuchs, and C. L. Liu, "A Parallel Algorithm for the Technology Mapping of LUT-based FPGAs," Proc. EUROPAR-96 Workshop on Parallel Nonnumerical Algorithms, Lyon, FRANCE, Aug. 1996.

 

  1. J. A. Chandy, S. Parkes, and P. Banerjee, "Distributed Object Oriented Data Structures and Algorithms for VLSI CAD," Proc. Workshop on Parallel Algorithms for Irregularly Structured Problems, Santa Barbara, CA, Aug. 1996.

 

  1. D. J. Palermo, E. W. Hodges, IV, and P. Banerjee, "Interprocedural Array Redistribution Data-Flow Analysis", Languages and Compilers for Parallel Computing, Santa Clara, CA, Aug. 1996.

 

  1. P. Prabhakaran and P. Banerjee, "Parallel Algorithms for Force-Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs," Proc. Int. Conf. Computer Design (ICCD-96), Austin, TX, Oct. 1996.

 

  1. D. Palermo, E. W. Hodges, and P. Banerjee, "Techniques for Selecting and Analyzing Data Distributions," Workshop on Challenges in Compiling for Scalable Parallel Systems, New Orleans, LA, Oct. 1996.

 

  1. K. McPherson and P. Banerjee, "Integrating Task and Data Parallelism in an Irregular Application: A Case Study", Proc. Symp. on Parallel and Distributed Processing, New Orleans, LA, Oct. 1996, pp. 208-213.

 

  1. V. Krishnaswamy, R. Gupta, P. Banerjee, "A Procedure for Software Synthesis from VHDL Models," Proc. of Asia-Pacific Design Automation Conf., Tokyo, JAPAN, Jan. 1997.

 

  1. G. Hasteer and P. Banerjee, "Simulated Annealing Based Parallel State Assignment for Finite State Machines," Proc. Int. Conf. VLSI Design (VLSI-97), Hyderabad, INDIA, Jan. 1997.

 

  1. D. Krishnaswamy, M. S. Hsiao, V. Saxena, E. M. Rudnick, P. Banerjee, and J. Patel,"Parallel Genetic Algorithms for Simulation-based Sequential Circuit Test Generation," Proc. Int. Conf. VLSI Design (VLSI-97),, Hyderabad, INDIA, Jan. 1997.

 

  1. J. G. Holm, S. Parkes, and P. Banerjee, "Performance Evaluation of a C++ Library Based Multithreaded System," Hawaii Int. Conf. on System Sciences, Maui, HA, Jan. 1997.

 

  1. S. Roy and P. Banerjee, "A Comparison of Parallel Approaches for Algebraic Factorization in Logic Synthesis", Proc. Int. Parallel Processing Symposium (IPPS97), Geneva, Switzerland, April 1997.

 

  1. Z. Xing, J. Chandy, and P. Banerjee, "Parallel Global Routing for Standard Cells," Proc. Int. Parallel Processing Symposium (IPPS-97), Geneva, Switzerland, April 1997.

 

  1. D. Krishnaswamy, E. Rudnick, P. Banerjee and J. Patel, "SPITFIRE: Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation," Proc. IEEE VLSI Test Symp., Monterey, CA, Apr. 1997.

 

  1. S. Roy and P. Banerjee, "An L-Shaped Partitioning-Based Algebraic Factorization Algorithm Proc. Int. Symp. on Circuits and Systems (ISCAS-97), Hong Kong, Jun. 1997.

 

  1. D. Krishnaswamy, P. Banerjee, E. Rudnick and J. Patel, "Asynchronous Parallel Algorithms for Test Set Partitioned Parallel Fault Simulation," Proc. Workshop on Parallel and Distributed Simulation (PADS97), Jun. 1997.

 

  1. G. Hasteer, A. Mathur, P. Banerjee, "An Efficient Assertion Checker for Combinational Properties," Proc. Design Automation Conference (DAC97), Jun. 1997.

 

  1. J. G. Holm, J. Chandy, G. Hasteer, V. Krishnaswamy, S. Parkes, S. Roy, and P. Banerjee, "Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General-Purpose Multiprocessors," Proc. International Conference on Supercomputing (ICS-97), Vienna, AUSTRIA, July 1997.

 

  1. D. Krishnaswamy and P. Banerjee, "Exploiting Task and Data Parallelism in Parallel Hough and Radon Transforms," Proc. Int. Conference on Parallel Processing (ICPP-97), Bloomingdale, IL, Aug. 1997.

 

  1. V. Krishnaswamy, G. Hasteer, and P. Banerjee, "Load Balancing and Workload Minimization of Overlapping Parallel Tasks," Proc. Int. Conference on Parallel Processing (ICPP-97), Bloomingdale, IL, Aug. 1997.

 

  1. J. A. Chandy and P. Banerjee, "A Parallel Circuit-Partitioned Algorithm for Timing-driven Standard Cell Placement," Proc. Int. Conference on Computer-Design (ICCD-97), October 1997, Austin, TX.

 

  1. G. Hasteer, A. Mathur, and P. Banerjee, "A Framework for Equivalence Checking of Multi-Phase FSMs," Proc. International High-Level Design Validation and Test Workshop, Oakland, CA, Nov. 1997.

 

  1. P. Prabhakaran and P. Banerjee, "Simultaneous Scheduling, Binding and Floorplanning in High-Level Synthesis," Proc. 11th International Conference on VLSI Design (VLSI Design'98), Chennai, India, Jan. 1998.

 

  1. S. Roy, P. Banerjee and M. Sarrafzadeh, "Partitioning Sequential Circuits for Low Power," Proc. 11th International Conference on VLSI Design (VLSI Design'98), Chennai, India, Jan. 1998.

 

  1. S. Roy, A. Harm, and P. Banerjee, "PowerShake: A Low Power Driven Clustering and Factoring Method ology for Boolean Expressions," Proc. Design, Automation and Test in Europe Conference (DATE 98), Paris, France, Feb. 1998.

 

  1. D. Chakrabarti, A. Lain, and P. Banerjee, "Evaluation of Compiler and Runtime Library Approaches for Supporting Parallel Regular Applications," Proc. Int. Parallel Processing Symp. (IPPS-98), Apr. 1998, Orlando, FL, pp. 74-79.

 

  1. M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, N. Shenoy, "A Generalized Framework for Global Communication Optimization," Proc. Int. Parallel Processing Symp. (IPPS-98), Apr. 1998, Orlando, FL, pp. 69-73.

 

  1. Z. Xing and P. Banerjee, "A Parallel Algorithm for Zero Skew Clock Tree Routing," Proc. Int. Symp. Physical Design (ISPD98), Apr. 1998, Monterey, CA.

 

  1. S. Roy and P. Banerjee, "Resynthesis of Sequential Circuits for Low Power," Proc. International Conference on Circuits and Systems (ISCAS-98), Monterey, CA, May 1998.

 

  1. P. Prabhakaran and P. Banerjee, "Parallel Algorithms for Scheduling, Binding, and Floorplanning in High -Level Synthesis," Proc. International Conference on Circuits and Systems (ISCAS-98), Monterey, CA, May 1998.

 

  1. G. Hasteer, A. Mathur, and P. Banerjee, "An Implicit Algorithm for Finding Steady States and its Application to FSM Verification," Proc. Design Automation Conference (DAC-98), Jun. 1998, San Francisco, CA.

 

  1. V. Kim and P. Banerjee, "Parallel Algorithms for Power Estimation," Proc. Design Automation Conference (DAC-98), Jun. 1998, San Francisco, CA.

 

  1. M. Wang, M. Sarrafzadeh, and P. Banerjee, "Placement with Incomplete Data," Proc. Design Automation Conference (DAC-98), Jun. 1998, San Francisco, CA.

 

  1. V. Krishnaswamy and P. Banerjee, "Parallel Compiled Event Driven VHDL Simulation," Proc. Int. Conf. Supercomputing (ICS-98), Melbourne, AUSTRALIA, July 1998.

 

  1. D. R. Chakrabarti, N. Shenoy, A. Choudhary, and P. Banerjee, "An Efficient Uniform Run-time Scheme for Mixed Regular-Irregular Applications," Proc. Int. Conf. Supercomputing (ICS-98), Melbourne, AUSTRALIA, July 1998, pp. 61-68.

 

  1. M. Kandemir, A. Choudhary, N. Shenoy, J. Ramanujam, and P. Banerjee, "A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests," Proc. Int. Conf. Supercomputing (ICS-98), Melbourne, AUSTRALIA, July 1998, pp. 69-75.

 

  1. M. Kandemir, J. Ramanujam, A. Choudhary, P. Banerjee, "An iteration space transformation algorithm based on an explicit data layout representation for optimizing locality," Proc. Workshop on Languages and Compilers for Parallel Computing (LCPC-98), Chapel Hill, NC, Aug. 1998.

 

  1. M. Kandemir, N. Shenoy, P. Banerjee, J. Ramanujam, and A. Choudhary, "Minimizing Data and Synchronization Costs in One-Way Communication," Proc. Int. Conf. Parallel Processing (ICPP98), Minneapolis, MN, Aug. 1998.

 

  1. Z. Xing and P. Banerjee, "A Parallel Algorithm for Timing-Driven Global Routing for Standard Cells," Proc. Int. Conf. Parallel Processing (ICPP98), Minneapolis, MN, Aug. 1998, pp. 54-61.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, N. Shenoy, and P. Banerjee, "Enhancing Spatial Locality Using Data Layout Optimizations," Proc. European Conference on Parallel Processing (Euro-Par'98), Southampton, ENGLAND, Sept. 1998, pp. 180-188.

 

  1. A. Mishra and P. Banerjee, "A Fault Tolerant Multi-Grid Algorithm," Proc. Parallel and Distributed Computing Systems (PDCS98), Chicago, Sep. 1998.

 

  1. S. Roy, A. Harms and P. Banerjee, "A Low Power Logic Optimization Methodology Based on a Fast Power Driven Mapping," Proc. Int. Conf. Computer Design (ICCD-98), Austin, TX, Oct. 1998.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, N. Shenoy, and P. Banerjee, "A Matrix-Based Approach to the Global Locality Optimization Problem," Proc. Parallel Architectures and Compilation Techniques (PACT-98), Paris, FRANCE, Oct. 1998.

 

  1. S. Roy and P. Banerjee, "Power Drive: A fast, canonical POWER estimator for DRIVing synthEsis," Proc. 1998 International Conference on Computer-Aided Design (ICCAD-98), San Jose, CA, Nov. 1998.

 

  1. G. Hasteer, A. Mathur, and P. Banerjee, "Efficient Equivalence Checking of Multi-Phase Designs Using Retiming", Proc. 1998 International Conference on Computer-Aided Design (ICCAD-98), San Jose, CA, Nov. 1998.

 

  1. D. Chakrabarti, P. Joisha, J. Chandy, D. Krishnaswamy, V. Krishnaswamy, and P. Banerjee, "WADE: A Web-Based Automated Parallel CAD Environment," Proc. International Conference on High Performance Computing (HiPC'98), Chennai, INDIA, Dec. 1998.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "Improving Locality Using Loop and Data Transformations in an Integrated Framework" Proc. 31st International Symposium on Micro-Architecture (MICRO-31), Dallas, Texas, Dec. 1998.

 

  1. P. Prabhakaran, J. Crenshaw, P. Banerjee, and M. Sarrafzadeh, "Simultaneous Scheduling, Binding and Floorplanning for Interconnect Power Optimization," Proc. 1999 VLSI Design Conference, Goa, INDIA, Jan. 1999.

 

  1. Y. Yuan and P. Banerjee, "ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment," Proc. 9th Great Lakes Symposium on VLSI, Ann Arbor, MI, March 1999.

 

  1. J. Crenshaw, M. Sarrafzadeh, P. Banerjee, and P. Prabhakaran, "An Incremental Floor-Planner," Proc. 9th Great Lakes Symposium on VLSI, Ann Arbor, MI, March 1999.

 

  1. Y. Yuan and P. Banerjee, "Fast Potential Integrals for Signal Integrity Analysis," Proc. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU'99), Monterey, CA, March 1999.

 

  1. D. Chakrabarti and P. Banerjee, "A Novel Compilation Framework for Supporting Semi-Regular Distributions in Hybrid Applications," Proc. 1999 International Parallel Processing Symposium (IPPS'99), San Juan, Puerto Rico, April 1999, pp. 597-602.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality," Proc. 1999 International Parallel Processing Symposium (IPPS'99), San Juan, Puerto Rico, April 1999, pp. 738-743.

 

  1. P. Joisha and P. Banerjee, "PARADIGM (version 2.0): A New HPF Compilation System," Proc. 1999 International Parallel Processing Symposium (IPPS'99), San Juan, Puerto Rico, April 1999, pp. 609-615.

 

  1. Y. Yuan and P. Banerjee, "Incremental Capacitance Extraction and Its Application to Iterative Timing Driven Detailed Routing," 1999 International Symposium on Physical Design (ISPD-99), Monterey, CA, April 1999.

 

  1. J. Chen and P. Banerjee, "Parallel Construction Algorithms for BDDs," 1999 International Symposium on Circuits and Systems (ISCAS'99), Orlando, FL, June 1999.

 

  1. S. Roy, A. Harms, and P. Banerjee, "An ff-approximate Algorithm for Delay-Constraint Technology Mapping," Proc. 1999 Design Automation Conference (DAC'99), Jun. 1999.

 

  1. A. Mishra and P. Banerjee, "An Algorithm Based Error Detection Scheme for the Multigrid Method," Proc. of the 1999 International Symposium on Fault Tolerant Computing, Madison, WI, June 15-18, 1999.

 

  1. M. Kandemir, P. Banerjee, A. Choudhary, J. Ramanujam, and E. Ayguade, "An ILP Approach for Optimizing Cache Locality," 1999 ACM International Conference on Supercomputing (ICS'99), Rhodes, Greece, June 1999.

 

  1. D. Chakrabarti and P. Banerjee, "Accurate Data and Context Management in Message Passing Programs," Proc. Languages and Compilers for Parallel Computing (LCPC-99), La Jolla, CA, Aug. 1999.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "A Framework for Interprocedural Locality Optimization Using Both Loop and Data Layout Transformations," Proc. 1999 International Conference on Parallel Processing (ICPP'99), Aizu, JAPAN, Sept. 1999, pp. 95-102.

 

  1. M. Kandemir, A. Choudhary, J. Ramanujam, and P. Banerjee, "On Reducing False Sharing While Improving Locality on Shared Memory Multiprocessors," Proc. 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT'99), Newport Beach, CA, Oct. 12-16, 1999.

 

  1. S. Periyayacheri, A. Nayak, A. Jones, N. Shenoy, A. Choudhary, and P. Banerjee, "Library Functions in Reconfigurable Hardware for Matrix and Signal Processing Operations in MATLAB," 11th IASTED Parallel and Distributed Computing and Systems Conference (PDCS'99), Cambridge, MA, Nov. 1999.

 

  1. Y. Yuan and P. Banerjee, "A Parallel 3-D Capacitance Extraction Program ," Proc. 6th International Conference on High Performance Computing (HiPC'99), Calcutta, INDIA, Dec. 1999.

 

  1. Z. Ye, N. Shenoy, and P. Banerjee, "A C Compiler for a Processor with a Reconfigurable Functional Unit," Proc. ACM/SIGDA Symposium on Field Programmable Gate Arrays, Monterey, CA, Feb. 2000.

 

  1. N. Shenoy, A. Choudhary, and P. Banerjee, "A System-Level Synthesis Algorithm with Guaranteed Solution Quality," Proc. Design Automation and Test in Europe (DATE 2000), Paris, FRANCE, March 27-30, 2000.

 

  1. M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee, "Parallel Algorithms for FPGA Placement," Proc. Great Lakes Symposium on VLSI (GVLSI 2000), Chicago, IL, March 2000.

 

  1. P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, and D. Zaretsky, "A MATLAB Compiler for Distributed Heterogeneous Reconfigurable Computing Systems," Int. Symp. on FPGA Custom Computing Machines (FCCM-2000), Napa Valley, CA, Apr. 2000.

 

  1. Y. Yuan and P. Banerjee, "A Parallel Implementation of A Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers," Proc. 14th International Parallel and Distributed Processing Symposium (IPDPS 2000), Cancun, MEXICO, May 1-5, 2000 (Best Paper Award).

 

  1. Z. Ye, P. Banerjee, S. Hauck, and A. Moshovos, "CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit," Proc. 27th International Symposium on Computer Architecture, Vancouver, CANADA, June 10-14, 2000.

 

  1. P. Joisha, A. Kanhere, P. Banerjee, N. Shenoy, and A. Choudhary, "Handling Context-Sensitive Syntactic Issues in the Design of a Front-end for a MATLAB Compiler," Proc. ACM Array Programming Languages Conference (APL-Berlin-2000), Berlin, GERMANY, July 24-27, 2000.

 

  1. A. Nayak, M. Haldar, A. Kanhere, P. Joisha, N. Shenoy, A. Choudhary, and P. Banerjee, "A Library Based Compiler to Execute MATLAB Programs on a Heterogeneous Platform," Proc. ISCA 13th International Conference on Parallel and Distributed Computing Systems (PDCS-2000), Las Vegas, NE, Aug. 8-10, 2000.

 

  1. A. Nayak, P. Banerjee, C. Chen, and M. Sarrafzadeh, "Power Optimization Issues in Dual Voltage Design," International Conference on Design Automation (ICDA 2000), Beijing, CHINA, Aug. 21-25, 2000.

 

  1. M. Haldar, A. Nayak, A. Kanhere, P. Joisha, N. Shenoy, A. Choudhary, and P. Banerjee, "MATCH Virtual Machine: An Adaptive Runtime System to Execute MATLAB in Parallel," Proc. International Conference on Parallel Processing (ICPP-2000), Toronto, CANADA, Aug. 2000.

 

  1. V. Kim, P. Banerjee, and K. De, "Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations," Proc. International Conference on Parallel Processing (ICPP-2000), Toronto, CANADA, Aug. 2000.

 

  1. P. Joisha, and P. Banerjee, "Efficient Computation of Ownership Sets in HPF," Proc. Languages and Compilers for Parallel COmputing (LCPC-2000), Aug. 2000, Yorktown Heights, New York.

 

  1. Y. Yuan and P. Banerjee, "Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors," Proc. International Conference on Computer Design (ICCD'2000), Austin, TX, Sept. 17-20, 2000.

 

  1. A. Nayak, M. Haldar, P. Banerjee, C. Chen, and M. Sarrafzadeh, "Power Optimization of Delay Constrained Circuits," Proc. Application Specific Integrated Circuit/System-on-a-Chip Conference (ASCI/SOC 2000), Washington, DC, September 2000.

 

  1. V. Kim, P. Banerjee, K. De, and J. Brouwers, "Parallel and Distributed VLSI Synthesis for Commercial CAD on a Network of Workstations," Proc. 12th IASTED International Conference on Parallel and Distributed Computing Systems (PDCS 2000), Las Vegas, NV, November 6-9, 2000.

 

  1. M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee, "Scheduling Alogorithms for Automated Synthesis of Pipelined Designs on FPGAs for Applications Described in MATLAB", Proc. International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES 2000), Nov. 2000, San Jose, CA.

 

  1. M. Haldar, A. Nayak, N. Shenoy, A. Choudhary, and P. Banerjee, "FPGA Hardware Synthesis from MATLAB," Proc. of VLSI Design Conf. Jan. 2001, Bangalore, India.

 

  1. N. Shenoy, P. Banerjee, A. Choudhary, and M. Kandemir, "Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators," Proc. of VLSI Design Conf. Jan. 2001, Bangalore, India.

 

  1. M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee, "Automated Synthesis of Pipelined Designs on FPGAs for Signal and Image Processing Applications Described in MATLAB," Proc. Asia Pacific Design Automation Conf (ASP-DAC), Feb. 2001, Tokyo, Japan.

 

  1. M. Haldar, A. Nayak, A. Choudhary, and P. Banerjee, ""FPGA Hardware Synthesis from MATLAB Utilizing Optimized IP Cores" Proc. Ninth ACM/SIGDA International Symposium on Field Programmable Gate Arrays., Feb. 2001, San Jose, CA.

 

  1. A. Nayak, M. Haldar, A. Choudhary, P. Banerjee, "Precision And Error Analysis Of MATLAB Applications During Automated Hardware Synthesis for FPGAs," Proc. Design Automation and Test in Europe (DATE 2001), Mar. 2001, Berlin, Germany.

 

  1. A. Nayak, M. Haldar, A. Choudhary and P. Banerjee, "Parallelization of MATLAB Applications for a Multi-FPGA System," Proc. FPGA Symp. on Custom Computing Machines (FCCM-2001), Napa Valley, CA, Apr. 2001.

 

  1. P. Joisha and P. Banerjee, "Correctly Detecting Intrinsic Type Errors in Typeless Languages Such as MATLAB," Proc. of the APL Conference, New Haven, CT, Jun. 2001.

 

  1. D. Chakrabarti and P. Banerjee, "Global Optimization Techniques for Automatic Parallelization of Hybrid Applications," Proc. Int. Conf. Supercomputing, Jun. 2001, Sorrento, Italy.

 

  1. P. G. Joisha, P. Banerjee, “Computing Array Shapes in MATLAB”,  Proc. of the Int. Workshop on Languages and Compilers for Parallel Computing (LCPC), Cumberland Falls, USA. August 2001. In Springer-Verlag Lecture Notes in Computer Science Series.

 

  1. A. K. Jones, and P. Banerjee, "Parallel Implementation of Matrix and Signal Processing Libraries on FPGAs," Proc. IASTED Parallel and Distributed Computing Systems Conf. (PDCS2001), Anaheim, CA, Aug. 2001.

 

  1. P. Banerjee, M. Haldar, A. Nayak, A. Choudhary, "Overview of the MATCH Compiler for Compiling MATLAB Programs into Hardware," Proc. of NASA Earth Science Technology Conference, Aug. 2001, Washington, DC.

 

  1. M. Haldar, A. Nayak, A. Choudhary, P. Banerjee, "A System for Synthesizing Optimized FPGA Hardware from MATLAB," Proc. Int. Conf. on Computer Aided Design, Nov. 4-8, 2001, San Jose, CA.

 

  1. A. Nayak, M. Haldar, A. Choudhary, and P. Banerjee, "Accurate Area and Delay Estimators for FPGAs," Proc. Design Automation and Test in Europe (DATE-2002), Mar. 2002, Paris, France.

 

  1. A. Jones, D. Bagchi, S. Pal, X. Tang, A. Choudhary, and P. Banerjee, "PACT HDL: A C Compiler with Power and Performance Optimizations," Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2002), Grenoble, France, October 2002.

 

205.                     P. Banerjee, M. Haldar, A. Nayak, V. Kim, D. Bagchi, S. Pal, N. Tripathi, “A Behavioral Synthesis Tool For Exploiting Fine Grain Parallelism in FPGAs,” Proc. International Workshop on Distributed Computing (IWDC), Dec. 28-30, 2002, Kolkata, INDIA. To Appear as Springer Verlag Lectures in Computer Science Series.

 

  1. P. Banerjee, "An Overview of a Compiler for Mapping MATLAB Programs onto FPGAs," Invited Paper at the Asia Pacific Design Automation Conference (ASP-DAC03), Jan. 2003, Japan.

 

  1.  P. Banerjee, M. Haldar, A. Nayak, V. Kim, J. Uribe, "AccelFPGA: A DSP Design Tool for Making Area Delay Tradeoffs While Mapping MATLAB Programs onto FPGAs,"  Proc.  International Signal Processing Conference (ISPC) and Global Signal Processing Expo (GSPx), Mar. 31-Apr. 3, 2003, Dallas, TX.

 

  1. P. Banerjee, V. Saxena, J. Uribe, M. Haldar, A. Nayak, V. Kim, D. Bagchi, S. Pal, N. Tripathi, R. Anderson, "Making Area-Performance Tradeoffs at the High Level Using the AccelFPGA Compiler for FPGAs," Proc.  11th ACM International Symposium on Field Programmable Gate Arrays (FPGA 03), Poster Paper.  Monterey, CA, Feb. 2003.

 

  1. P. G. Joisha, and P. Banerjee, "The MAGICA Type Inference Engine for MATLAB," Proc. International Conference on Compiler Construction (CC 03), Warsaw, Poland, Apr. 2003.

 

  1. P. Banerjee, D. Bagchi, M. Haldar, A. Nayak, V. Kim, R. Uribe, “Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design,” Proc. FPGA based Custom Computing Machines (FCCM), Apr. 2003, Monterey, CA.

 

  1.  A. K. Jones, P. Banerjee. An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs, Proc. FPGA based Custom Computing Machines (FCCM), Apr. 2003, Monterey, CA.

 

  1.  P. G. Joisha, P. Banerjee, “Static Array Storage Optimization in MATLAB,” Proc. ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation (PLDI 03), San Diego, CA, June 2003.

 

213.                      X. Tang, T. Jiang, A. K. Jones, P. Banerjee, “Compiler Optimizations in the PACT HDL Behavioral Synthesis Tool for ASICs and FPGAs,” Proc.  IEEE System on a Chip Conference, Portland, OR., Sep. 2003.

 

214.                     T. Jiang, X. Tang, A. K. Jones, P. Banerjee, “Optimizing Power While Exploiting Fine Grain Parallelism in  FPGAs” Proc.  Int. Conf. Parallel and Distributed Computing Systems (PDCS), Marina Del Rey, CA,  Nov. 2003.

 

215.                     R. Mukherjee, A. K. Jones, P. Banerjee, “System Level Synthesis of Multiple IP Blocks in the PACT Compiler,” Proc.  Int. Conf. Parallel and Distributed Computing Systems (PDCS03), Marina Del Rey, CA,  Nov. 2003

 

216.                     N. Liveris, P. Banerjee, “Power Aware Interface Synthesis for Bus Based SOC Design,” Proc.  Design Automation and Test in Europe (DATE 2004), Feb. 2004, Paris, FRANCE.

 

217.                     T. Jiang, X. Tang, P. Banerjee, “High Level Area, Delay and Power Estimation for FPGAs,”  Proc. Int. Conf. on Field Programmable Gate Arrays (FPGA-2004), Monterey, CA, Feb. 2004.

 

218.                     S. Roy, D. Sinha and P. Banerjee, “An Algorithm for Trading off Quantization Error  in  MATLAB based Hardware Design,” Proc. Int. Conf. on Field Programmable Gate Arrays (FPGA-2004), Monterey, CA, Feb. 2004.

 

219.                     R. Mukherjee, A. K. Jones, P. Banerjee, “Handling Data Streams While Compiling C Programs Onto Hardware” Proc. IEEE  Int. Symp. on VLSI (ISVLSI), Feb. 19-20, 2004; Lafayette, LA, USA

 

220.                     A. K. Jones, X. Tang, P. Banerjee, “Compile-time Simulation for Low-Power Optimization using SystemC,” Proc.  IASTED International Conference on Modeling and Simulation (MS 2004), March 2004, Marina del Rey, CA.

 

221.                     T. Jiang, X. Tang, P. Banerjee, “High Level Area and Power Estimation for FPGAs,”  Proc. Great Lakes Symp. on VLSI (GLSVLSI 2004), April 26-28, 2004, Boston, MA, USA.

 

222.                     D. Zaretsky, G. Mittal, X. Tang, P. Banerjee, “Evaluation of Scheduling and Allocation Algorithms While Mapping Software Assembly onto FPGAs,”  Proc.  Great Lakes Symp. on VLSI (GLSVLSI 2004), April 26-28, 2004, Boston, MA, USA.

 

223.                     D. Zaretsky, G. Mittal, X. Tang, and P. Banerjee, "Overview of the FREEDOM Compiler for Mapping DSP software to FPGAs," Proc. IEEE Conference on FPGA based Custom Computing Machines (FCCM), Napa Valley, Apr. 2004.

 

224.                     G. Mittal, D. Zaretsky, X. Tang, and P. Banerjee, "Automatic Translation of Software Binaries onto FPGAs," Proc. Design Automation Conference (DAC 2004), San Diego, Jun. 2004.

 

225.                     S. Roy and P. Banerjee, “An Algorithm for Converting Floating Point Computations to Fixed Point Computations in  MATLAB based Hardware Design,” Proc. Design Automation Conference (DAC 2004), San Diego, Jun. 2004.

 

226.                     P. Banerjee, G. Mittal, D. Zaretsky, X. Tang, “BINACHIP-FPGA: A Tool to Map DSP Software Binaries and Assembly Programs onto FPGAs,” Proc. Embedded Signal Processing Conference (GSPx), Sep. 2004, Santa Clara, CA.

 

227.                     X. Tang, T. Jiang, A. K. Jones, P. Banerjee, “Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation,” Proc.  18th International Conference on VLSI Design (VLSI 2005), Jan. 2005, Kolkata, India.

228.                     G. Mittal, D. Zaretsky, P. Banerjee, “Automatic Extraction of Function Bodies from Software Binaries ,” Proc. Asia Pacific Design Automation Conference (ASP-DAC 2005), Jan. 2005, Shanghai, China.

229.                     X. Tang, H. Zhou, and P. Banerjee, “Leakage Power Optimization with Dual Vth Library during High Level Synthesis,” Proc. IEEE/ACM Design Automation Conf, Jun. 2005, Anaheim, CA.

230.                     D. Zaretsky, G. Mittal, R. P. Dick and P. Banerjee, “Generation of Control and Data Flow Graphs from Scheduled Pipelined Assembly Code,” Proc. 18th Int. Workshop on Languages and Compilers for Parallel Computing (LCPC 2005), Oct. 2005, Hawthorne, NY.

231.                     G. Mittal, D. Zaretsky, and P. Banerjee, “Tool-flow For an Automated Compilation of SIMULINK and Real-Time Workshop Applications onto Heterogeneous Platforms,”  Proc. GSPx 2005 Pervasive Signal Processing Conference, Oct. 2005, Santa Clara, California,

232.                     N. Liveris, H. Zhou, P. Banerjee, “An Efficient System-level to RTL Verification Framework for Computation-Intensive Applications,” Proc. Asian Test Symposium, Dec. 18-21, 2005 in Kolkata, India.

233.                     D. Zaretsky, G. Mittal, R. P. Dick and P. Banerjee, “Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs,” Proc. Int. Symp. On VLSI Design (VLSI 2006), Jan. 2006, Hyderabad, INDIA.

234.                     A. Mallik, D. Sinha, H. Zhou, and P. Banerjee, "Smart Bit-width Allocation for Low Power Optimization in a SystemC based ASIC design Environment", Proc. Design Automation and Test in Europe (DATE), Mar. 2006, Munich, Germany.

 

 

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