Prith Banerjee received his B.Tech. degree in Electronics and Electrical Engineering from the Indian Institute of Technology, Kharagpur, India, in August 1981, and the M.S. and Ph.D degrees in Electrical Engineering from the University of Illinois at Urbana-Champaign in December 1982 and December 1984 respectively.

Dr. Banerjee is currently the Walter P. Murphy Professor and Chairman of the Department of Electrical and Computer Engineering, and Director of the Center for Parallel and Distributed Computing. at Northwestern University in Evanston, Illinois. Prior to that he was the Director of the Computational Science and Engineering program, and Professor of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign.

Prith Banerjee has also served as Founder, President and CEO of a company called AccelChip during 2000- 2002 while he was on leave from Northwestern University. This company was founded based on technology developed as part of a DARPA sponsored research on the MATCH compiler at Northwestern. Subsequently, he served AccelChip as Chief Scientist during 2002-2004.

Dr. Banerjee's research interests are in Parallel Algorithms for VLSI Design Automation, Distributed Memory Parallel Compilers, and Compilers for Adaptive Computing, and is the author of over 300 papers in these areas. He leads the PARADIGM compiler project for compiling programs for distributed memory multicomputers, the ProperCAD project for portable parallel VLSI CAD applications, the MATCH project on a MATLAB compilation environment for adaptive computing, and the PACT project on power aware compilation of hardware and software . He is also the author of a book entitled "Parallel Algorithms for VLSI CAD" published by Prentice Hall, Inc., 1994.

Dr. Banerjee has received numerous awards and honors during his career. He became a Fellow of the ACM in 2000. He was the recipient of the 1996 Frederick Emmons Terman Award of ASEE's Electrical Engineering Division sponsored by Hewlett-Packard. He was elected to the Fellow grade of IEEE in 1995. He received the University Scholar award from the University of Illinois for in 1993, the Senior Xerox Research Award in 1992, the IEEE Senior Membership in 1990, the National Science Foundation's Presidential Young Investigators' Award in 1987, the IBM Young Faculty Development Award in 1986, and the President of India Gold Medal from the Indian Institute of Technology, Kharagpur, in 1981.

Dr. Banerjee has served as the Program Chair of the High-Performance Computing Conference in 1999, and Program Chair of the Int. Conf. on Parallel Processing for 1995. He has served as General Chairman of the International Conference on Parallel and Distributed Computing Systems in 1997, and the International Workshop on Hardware Fault Tolerance in Multiprocessors, 1989. He has served on the Program and Organizing Committees of the 1988, 1989, 1993 and 1996 Fault Tolerant Computing Symposia, the 1992, 1994, 1995, 1996 and 1997 International Parallel Processing Symposium, the 1991, 1992, 1994 and 1998 International Symposia on Computer Architecture, the 1998 International Conference on Architectural Support of Programming Languages and Operating Systems, the 1990, 1993, 1994, 1995, 1996, 1997 and 1998 International Symposium on VLSI Design, the 1994, 1995, 1996, 1997, 1998 and 2000 International Conference on Parallel Processing, and the 1995, 1996 and 1997 International Conference on High-Performance Computing. He is an Associate Editor of the IEEE Transactions on Parallel and Distributed Systems, and IEEE Transactions on Computers. In the past he has served as Associate Editor of the Journal of Parallel and Distributed Computing, the IEEE Transactions on VLSI Systems, and the Journal of Circuits, Systems and Computers.

Prith has served on the Technical Advisory Board of many companies such as Ambit Design Systems, Calypto Design Systems, and Atrenta.

Prith has received research grants worth about $4.0 million during his 12 years at Illinois with him as a principal investigator. He has received about $8.0 million at Northwestern University during the past 4 years. His funding has come from national agencies such as DARPA, NSF, ONR, NASA and industries such as IBM, Intel, General Electric, and SRC.

He has completed the supervision of 33 Ph.D. and 39 M.S. students already, and is presently supervising 4 Ph.D. students.

SUMMARY OF RESEARCH

Professor Prith Banerjee has performed research on Parallel Algorithms, Parallel Compilers, and Parallel Architectures, and Compilers for Adaptive Computing. He has published over 300 papers in premier journals and conferences. In the following, his main research accomplishments are summarized.

(1) Parallel Algorithms for VLSI CAD. As VLSI circuits become more complex, the computational requirements for performing various CAD tasks increase almost exponentially. Professor Banerjee has investigated efficient parallel algorithms for various tasks in VLSI computer-aided design in order to reduce the runtimes of these tools for future billion transistor VLSI chips from weeks to hours. He has written a graduate level textbook on the subject, "Parallel Algorithms for VLSI CAD," published by Prentice Hall, 1994. As part of the PROPERCAD project, he has developed portable parallel algorithms that are suitable for execution on distributed memory message-passing multicomputers, networks of workstations, and shared-memory multiprocessors. His most significant publications in this area include his work on parallel simulated annealing algorithms for standard cell placement where he proposed and evaluated several parallel strategies such as parallel moves, speculative computation and multiple markov chains approaches. In his work on parallel algorithms for test generation of combinational and sequential circuits, he proposed how a parallel branch and bound algorithm for test generation can be efficiently integrated within a parallel fault simulation environment. He has worked on parallel circuit extraction and design rule checking, where he developed strategies for exploiting data parallelism on flattened layouts, and task parallelism on hierarchical layouts, and sophisticated scheduling for combining task and data parallelism. He has also worked on parallel algorithms for global and detailed routing using iterative improvement, parallel algorithms for combinational and sequential logic synthesis using the MIS and transduction algorithms, parallel algorithms for behavioral simulation using VHDL, and on parallel algorithms for high-level synthesis. Dr. Banerjee published more than 100 papers in this area; two of these papers have received the Best Paper Awards at conferences, one for his work on "SPITFIRE: Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation" at the IEEE VLSI Test Symposium in 1997, and another for his work on "A Parallel Implementation of A Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers" at the IEEE Int. Parallel and Distributed Symposium in 2000. Prith's work in this area was supported by DARPA, NSF, and the Semiconductor Research Corporation. He has worked closely with many companies including the Cadence, LSI Logic, Ambit Design Systems, and Sunrise Test Systems, to develop these parallel algorithms and have transferred many of these algorithms to industry. For example, LSI Logic has a commercial product called Parallel Gate-Ensemble which is based on the parallel cell placement algorithms developed by him. Cadence Design Systems has a product called parallel VAMPIRE which is based on some of the parallel design rule checking algorithms developed by him. Finally, he has worked with Ambit Design Systems to develop a product called Distributed Buildgates for parallel logic synthesis. The Design Sciences Program of the Semiconductor Research Corporation listed the ProperCAD project under Professor Banerjee as one of the two key Technical Innovations during the 1994 year, and was included in the SRC Corporate Annual Report. More information about the ProperCAD project can be found at: http:/www.ece.nwu.edu/cpdc/ProperCAD/pcad.html.

(2) Parallelizing Compilers. Distributed memory message passing machines such as the Intel Paragon, and the IBM SP-2 and networks of workstations offer significant advantages over shared-memory multiprocessors in terms of cost and scalability. Unfortunately, to extract all that computational power from these machines, users have to write efficient software for them, which is an extremely laborious process. As part of the PARADIGM compiler project, Prof. Banerjee has developed strategies by which sequential programs written in Fortran 77 or High Performance Fortran can be automatically parallelized and compiled for efficient execution on distributed memory message-passing multicomputers and networks of workstations. His most significant publications in this area include his work on automated data distribution on distributed memory multi-processors, where he developed a constraint-based approach for deriving the static and dynamic distributions of regular data structures using simple computation and communication cost models. He has also developed strategies where the PARADIGM compiler can automatically extract data and functional parallelism simultaneously from Fortran programs using a convex programming formulation. His other significant contribution is in the development of an uniform framework for supporting both regular and irregular data accesses using an interval based runtime library using the inspector-executor approach. He has recently developed strategies for unified loop and data transformations for improving cache locality in distributed shared memory multiprocessors. Prith's work on the PARADIGM compiler is one of five leading research projects in academia in this area of parallelizing compilers fordistributed memory multiprocessors; this includes Ken Kennedy's work on the Fortran D compiler at Rice, Monica Lam's work on SUIF at Stanford, Joel Saltz's work on CHAOS/PARTI at Maryland, David Padua's work on the Polaris compiler at Illinois, and Hans Zima's work on the Vienna Fortran compiler in Europe. Prith's work has been supported by DARPA, NSF and various companies. He has published more than 80 papers in this area (out of 270 total papers in his career), one of which received a Best Paper Award at the International Conference on Parallel Processing in 1994 for the paper entitled "Communication Optimizations for Distributed Memory Multicomputers in the PARADIGM Compiler." He has worked closely with many companies including IBM, Kuck and Associates, and Portland Group, to develop various compiler techniques, and has transferred many of these techniques to industry. Specifically, the automatic data partitioning and static cost estimation work was transferred to IBM T.J. Watson Center (by Manish Gupta) in the IBM xlf HPF compiler. The PARADIGM compiler has been licensed to a company, Tata Information Systems Ltd., for commercial development. More information about the PARADIGM project can be found at:  http:/www.ece.nwu.edu/cpdc/Paradigm/Paradigm.html

(3) MATLAB Compiler for Reconfigurable Computing. Digital signal processing and image processing applications are typically written in the MATLAB programming language, and are typically executed on general purpose DSP processors.  However, recently DSP algorithms are being mapped onto Reconfigurable Field Programmable Gata Arrays (FPGAs) for performance and reconfigurability reasons.  However, to map DSP algorithms onto FPGAs, users are required to manually translate MATLAB programs onto languages such as VHDL or Verilog.  As part of the MATCH project, Professor Banerjee has the MATCH compiler that takes MATLAB programs and automatically parallelizes it and maps it a heterogeneous environment of off-the-shelf embedded processors, digital signal processors, and FPGAs. More details of the MATCH project can be found at the URL: http://www.ece.nwu.edu/cpdc/Match/Match.html.  He  has transferred this technology to a new company he has founded called Accelchip (www.accelchip.com) which has developed a successful product called AccelFPGA based on the MATCH compiler.

(4) Compiler for Power Aware Computing. Low power electronic circuits are becoming very desirable in the domain of mobile wireless devices.  Current electronic design tools have two limitations: (1) They require the designers to enter their designs at the register transfer level in languages such as VHDL or Verilog (2) They perform area minimizations under timing constraints or perform timing optimizations under area constraints. As part of the PACT compiler project, Prith Banerjee is developing a  compiler that will take a high-level language, namely, C, and automatically produce Register Transfer Level VHDL and Verilog code that can be mapped onto FPGAs and ASICs.  Furthermore, this transformation will be performed under power, area and timing constraints. More details of the MATCH project can be found at the URL: http://www.ece.nwu.edu/cpdc/PACT/PACT.html

(5) Compiling Software Binaries onto Hardware.  Increasing demands for cell-phones, PDAs, and network devices have provided opportunities for the growth of embedded software, operating systems and development tools.  As newer processor architectures are announced, there is a need to reuse and migrate the software from older generation processors to newer processors.  In this research we will develop automated compiler algorithms to translate software binary and assembly code of a general-purpose processor into Register Transfer Level VHDL and Verilog code to be mapped onto hardware in the form of FPGAs and ASICsWe further plan to study techniques for performing hardware/software co-design and verification on integrated Systems-on-a-Chip (SOC) platforms consisting of embedded processors, memories, FPGAs and ASICs. We are demonstrating our concepts using a prototype FREEDOM compiler that will translate binary code of a Texas Instruments TMS320 C6000 processor into a hardware/software implementation on a Xilinx Virtex II Pro SOC.  More details of the FREEDOM project can be found at the URL: http://www.ece.nwu.edu/cpdc/FREEDOM/FREEDOM.html

CONTRIBUTIONS AS AN ADMINISTRATOR

Prith Banerjee has had wide ranging experience as an administrator.  He has served as
 
• Director the Computational Science and Engineering Program at the University of Illinois from 1994 to 1996.
 
• Director of the Center for Parallel and Distributed Computing at Northwestern University from 1996-present
 
• Chairman of the Electrical and Computer Engineering department at Northwestern University from 1998-2001 and 2002-present
 
• President and CEO of AccelChip from 2000 to 2002.
 

In the following his contributions as an administrator will be described in more detail.

Prith Banerjee was instrumental in the development of a new graduate program at the University of Illinois called Computational Science and Engineering. The term Computational Science and Engineering (CSE) refers to those activities in science and engineering that exploit computing as their main tool. The purpose of the graduate option in CSE at the University of Illinois was to develop an academic program that prepares students with an interdisciplinary background in numerical computing, high performance software and parallel computing, and computational aspects of various applications. Prof. Banerjee was the founding Director of the CSE program at Illinois during 1994-96. During those two years, he was successful in establishing the CSE academic program in ten departments, creating/identifying more than 40 CSE courses, sponsoring 8 research assistantships for CSE research activities, writing research proposals to obtain advanced computing equipment for a CSE laboratory, starting a CSE seminar, and writing proposals to acquire grants for research in CSE. Through his efforts, he was able to procure the donation of 10 workstations from IBM, and a 24 processor Paragon multiprocessor from Intel, a SUN Sparcserver 8 processor multiprocessor, and a dozen SUN workstations.

Since Sep. 1, 1996, Prof. Banerjee has been the Director of the Center for Parallel and Distributed Computing at Northwestern University. The Center has 11 faculty from Northwestern and two scientists from Argonne National Lab. The Center has attracted three large DARPA grants worth about $2 million each, namely the MATCH compiler project, the CHIMAERA project, and the PACT compiler project.   In addition, he has brought in a $1 million NSF grant on the PANTHER project, and a $1 million DOE grant to support research on a wide range of topics in high-performance computing. 

During Sep. 1, 1998 to Aug. 31, 2001, and from September 1, 2002 to present, Prof. Banerjee has been the Chairman of the Electrical and Computer Engineering Department at Northwestern University. During these five years, he has led the development of some innovative revisions of the electrical engineering and computer engineering undergraduate curricula at Northwestern. He has been responsible for leading the creation of two freshman courses ECE 202 on "Introduction to Electrical Engineering" and ECE 203 on "Introduction to Computer Engineering". The ECE 202 course teaches electrical engineering to freshman students using the design of a CD player, and the ECE 203 course teaches computer engineering to freshmen using the design of an autonomous robot. During 1998-99, he personally attended weekly meetings of two committees, the undergraduate electrical engineering committee, and the undergraduate computer engineering committee, which designed the new curriculum and the courses. He has also been instrumental in making major renovations in the instructional labs of the department by securing equipment donations from companies such as Hewlett-Packard, Motorola and Microsoft, and obtaining significant funding from the President of Northwestern University.  In addition, he was instrumental in hiring 11 new faculty in the department (including 2 women), 6 of whom have won the NSF CAREER awards.  During this period the rankings of the ECE Department have gone up to 17th in Computer Engineering and 20th in Electrical Engineering according  to US News and World Reports.

CONTRIBUTIONS AS AN ENTREPRENEUR

Dr. Banerjee has founded a company called AccelChip, located in Schaumburg, Illinois (www.accelchip.com) in July 2000. He served as its Founder, President and CEO until June 2002. During July, 2002 to June 2004, he transitioned to the role of Chief Scientist in a part time consulting role. The company has developed its first product called AccelFPGA which takes MATLAB and SIMULINK versions of DSP applications and map into field programmable gate arrays (FPGAs) This technology is based on the MATCH compiler technology developed at Northwestern University. Over the past two years he has hired a top management team, has raised $2.3 million in Venture Capital funding, and produced over $800,000 in revenues of its products, and grown the company to more than 20 employees. He was on leave from Northwestern University during 2001-2002, and has gone back to Northwestern as Chairman of the ECE department effective September 1, 2002.